Dual Shift Register Layout for LCD Gate Driver Area Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Large LCD devices face issues with image quality due to increased propagation delay of gate driving voltage in lengthened gate lines, and the existing gate drivers occupy a significant area, making it difficult to mount them within limited design spaces.
Innovation Solution
A dual shift register is introduced, comprising two sets of stages that output scan pulses using sequential and circular phases of clock signals, allowing for forward and reverse direction voltage application, which reduces the area occupied by the gate driver and maintains image quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the gate driver is mounted on the LCD panel, then the gate driving function is integrated, but the occupying area increases significantly
Solution Approach 1:
The gate driver is divided into multiple stages (first stage, second stage, third stage, fourth stage) that are distributed across different locations on the LCD panel. Each stage independently generates scan pulses for specific gate lines, eliminating the need for a single large centralized gate driver while achieving full gate driving functionality.
2Device complexity
If a single shift register is used, then the structure is simple, but the occupying area is large and cannot be mounted within limited design area
Solution Approach 1:
The single shift register is segmented into multiple smaller shift register stages distributed at different locations. Each stage has its own flip-flops and switching elements, reducing the area required for each individual stage while collectively providing the complete scanning function across the panel.
Solution Approach 2:
Instead of placing all shift register stages in a single linear sequence occupying large area, the stages are distributed in a two-dimensional arrangement across the panel (top, bottom, left, right sides), utilizing spatial distribution to reduce overall footprint.
3Length of stationary object
If gate lines are lengthened for enlarged LCD devices, then the display size increases, but the propagation delay of gate driving voltage increases
Solution Approach 1:
The gate driving function is segmented into multiple distributed stages positioned at different locations along the gate lines. This segmentation creates multiple shorter signal paths instead of one long path, reducing the maximum propagation distance and delay for gate driving voltage across the enlarged panel.
Data Source
AI summary
Disclosed is a dual shift register that includes a first shift register configured to include a plurality of stages which sequentially output scan pulses using at least two clock signals with sequential and circular phases, and a second shift register configured to a plurality of stages which form pair with the respective stages of the first shift register and sequentially output the scan pulses using at least two clock signals. Each stage includes: a scan direction controller configured to respond to the scan pulses from previous and next stages and to selectively output forward and reverse direction voltages with opposite electric potentials to each other; and an output portion configured to respond to the output signal of the scan direction controller, to generate two sequential scan pulses using two of the at least two clock signals, and to distribute the sequential scan pulses to the previous and next stages.