Staggered Dual-Side Chip Interconnect Layout for Shorter PCB Routing
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Solution Overview
Problem
As process nodes shrink and clock speeds increase, the insertion loss and crosstalk noise introduced by net routing path lengths on printed circuit boards worsen, particularly limiting performance in inter-chip communication due to physical constraints and competing demands for routing distances and transient power delivery.
Innovation Solution
The layout of chip packages on printed circuit boards is optimized with a stacked and staggered mounting configuration, where low-latency pins are concentrated along a single side, allowing for direct routing connections and accommodating decoupling capacitors and power modules, thereby minimizing routing distances and ensuring rapid power delivery.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If chips are mounted on the same side of a PCB, then layout flexibility is maintained, but inter-chip path length increases causing insertion loss and crosstalk noise
Solution Approach 1:
The patent transitions from two-dimensional same-side mounting to three-dimensional stacked mounting on opposite sides of the PCB. This dimensional change allows chips to be positioned directly across from each other through the board thickness, dramatically reducing inter-chip path length while maintaining layout flexibility through the stacked configuration
2Length of stationary object
If chips are mounted on opposite sides of a PCB, then inter-chip path length is minimized, but placement of other components becomes constrained
Solution Approach 1:
The patent segments the PCB into distinct regions: interconnect regions for direct chip-to-chip routing and non-interconnect regions for other components. This segmentation allows components to be placed in dedicated areas without interfering with the minimized inter-chip paths, resolving the constraint issue
3Loss of time
If routing path length is reduced for high-speed communication, then signaling latency decreases, but space for power delivery components and thermal management becomes limited
Solution Approach 1:
By stacking chips on opposite sides of the PCB, the patent creates vertical space utilization that frees up horizontal routing areas. This allows dedicated regions to be allocated for power delivery networks and thermal management components without increasing the inter-chip communication path length
Solution Approach 2:
The PCB is segmented into interconnect regions for signal routing and non-interconnect regions for power and thermal components. This segmentation enables simultaneous optimization of signaling paths and allocation of sufficient space for power delivery and thermal management
Data Source
AI summary
Layout techniques for chip packages on printed circuit boards are disclosed that address the multivariate problem of minimizing routing distances for high-speed I/O pins between chip packages while simultaneously providing for the rapid provision of transient power demands to the chip packages. The layout techniques may also enable improved thermal management for the chip packages.