Dual-Side Stacked CMOS Layout Without Fine Vertical Contacts
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Solution Overview
Problem
Current stacked FET approaches face challenges in locally wiring the bottom device to the top or vice versa, leading to poor performance or larger cell size, and struggle to produce stacked FETs with multiple threshold voltages due to misalignment and the need for fine contacts.
Innovation Solution
The proposed solution involves a dual side stacked transistor structure with upper and lower CMOS transistor layers interconnected through frontside and backside interconnect layers, respectively, allowing for conductive interconnections at peripheral regions and eliminating the need for top-to-bottom or bottom-to-top contacts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If extremely small contacts are used to save area for scaling and reduce parasitic capacitance, then area and parasitic capacitance are reduced, but performance deteriorates
Solution Approach 1:
The patent transitions from vertical stacking with direct top-to-bottom contacts to a planar arrangement where upper and lower CMOS layers are positioned side-by-side. This dimensional change eliminates the need for deep vertical contacts while maintaining electrical connectivity through lateral interconnects, thereby preserving both area efficiency and device performance.
Solution Approach 2:
The patent introduces intermediate interconnect layers and via structures that mediate the connection between upper and lower CMOS devices. Instead of requiring direct contact between stacked devices, these intermediary elements provide robust electrical pathways that maintain performance while allowing for larger, more reliable contact areas.
2Reliability
If robust contact size and contact spacing are used, then performance is improved, but cell size increases
Solution Approach 1:
By arranging upper and lower CMOS layers in a planar configuration rather than vertically stacked, the patent eliminates the need for large vertical contact structures. The interconnect paths are distributed across multiple planar layers, allowing robust connections without increasing the footprint of the cell.
Solution Approach 2:
The patent divides the interconnection function across multiple separate interconnect layers and via structures. Instead of relying on a single large contact, the connection is segmented into multiple smaller via contacts distributed across different metal layers, achieving both robustness and area efficiency.
3Adaptability or versatility
If bonded flow is used to produce stacked FETs with multiple threshold voltages, then multiple Vt are achieved, but misalignment destroys process margin
Solution Approach 1:
The patent transitions from vertical stacking (requiring precise top-to-bottom alignment) to a planar arrangement where upper and lower CMOS layers are positioned side-by-side. This dimensional change eliminates the alignment sensitivity issue, as lateral positioning is less critical than vertical overlay precision in bonded flows.
Solution Approach 2:
The patent separates the formation of upper and lower CMOS devices into distinct processing steps that can be independently optimized. By segmenting the device formation process and using separate interconnect layers, the patent reduces the cumulative alignment errors that would otherwise destroy process margin in vertically stacked structures.
4Productivity
If fine contacts are made through top to bottom at very tight pitches, then device density is improved, but manufacturing complexity and difficulty increase
Solution Approach 1:
The patent replaces complex deep vertical contacts with planar interconnect paths distributed across multiple metal layers. This dimensional change simplifies the contact formation process by eliminating the need to drill or etch through the entire device thickness, thereby reducing manufacturing complexity while maintaining high device density.
Solution Approach 2:
The patent segments the interconnection path into multiple smaller via contacts across different metal layers rather than requiring a single long vertical contact. This segmentation reduces the pitch and alignment requirements for each individual via, making the overall process more manufacturable while achieving the same density.
Data Source
AI summary
A semiconductor structure includes an upper-level CMOS transistor layer having a plurality of upper-level N-type and P-type field effect transistors; and a frontside interconnect layer above, and interconnected with, the upper-level transistor layer. The frontside interconnect layer includes frontside power rails and frontside signal wiring, and at least three frontside interconnect layer metal levels. A lower-level CMOS transistor layer has a plurality of lower-level N-type and P-type field effect transistors; and a backside interconnect layer below, and interconnected with, the lower-level transistor layer. The backside interconnect layer includes backside power rails and backside signal wiring and at least three backside interconnect layer metal levels. At a peripheral region of the structure, at least one conductive interconnection is provided between a third or higher of the at least three frontside interconnect layer metal levels and a third or lower of the at least three backside interconnect layer metal levels.