Dual-Side Cut Stacked FET Structure for Backside Power Access
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Solution Overview
Problem
Nanosheet technology faces challenges in scaling down due to device interference and difficulty in forming connections to a backside power network as devices become smaller and closer together.
Innovation Solution
A semiconductor device structure is developed with offset upper and lower active regions across upper and lower transistors, featuring frontside and backside dielectric pillars and fills to facilitate improved connectivity and reduce interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If nanosheet devices are scaled down and placed closer together to increase device density, then device integration density is improved, but device interference increases and connection formation to backside power network becomes more difficult
Solution Approach 1:
The patent introduces a third dimension by forming dielectric pillars extending from the frontside to the backside of the substrate. These pillars create vertical pathways that enable backside power network connections without increasing lateral device density, thus resolving the interference issue while maintaining high integration density.
Solution Approach 2:
The dielectric pillars act as intermediary structures that facilitate electrical connections between the frontside active regions and the backside power network. By introducing these intermediate elements, the patent enables power delivery without requiring direct lateral proximity between devices, thereby reducing device interference.
2Productivity
If nanosheet devices are scaled down and placed closer together to increase device density, then device integration density is improved, but difficulty in forming connections to backside power network increases
Solution Approach 1:
The patent transitions from two-dimensional lateral connections to three-dimensional vertical connections by forming dielectric pillars that extend through the substrate thickness. This dimensional change simplifies connection formation by providing direct vertical pathways to the backside power network, eliminating the need for complex lateral routing at scaled dimensions.
Solution Approach 2:
The dielectric pillars are formed in advance during the fabrication process, creating pre-established connection pathways before final device assembly. This preliminary action simplifies subsequent manufacturing steps by providing ready-made vertical channels for power network integration.
3Adaptability or versatility
If offset active regions with dielectric pillars are implemented to reduce device interference and enable backside connections, then device scalability is improved, but device structure complexity increases
Solution Approach 1:
The patent segments the device structure into distinct functional components: frontside active regions, dielectric pillars, and backside power network. This segmentation allows each component to be optimized independently and simplifies the overall design by breaking down the complex integrated structure into manageable segments that can be manufactured and analyzed separately.
Solution Approach 2:
The dielectric pillars serve multiple functions simultaneously: they provide mechanical support, enable electrical connections to the backside power network, and reduce device interference through their offset configuration. This multi-functionality reduces overall structure complexity by combining multiple roles into a single element.
Data Source
AI summary
According to the embodiment of the present invention, a semiconductor device includes a plurality of nanodevices including a plurality of upper transistors and a plurality of lower transistors. The plurality of nanodevices include an upper active region and a lower active region that are offset from each other across the plurality of upper transistors and the plurality of lower transistors. A first frontside gate cut dielectric pillar is located adjacent to and parallel to a first nanodevice of the plurality of nanodevices along an x-axis. A backside surface of the first frontside gate cut dielectric pillar extends a first width along a y-axis. A first backside dielectric fill is in direct contact with the backside surface of the first frontside gate cut dielectric pillar. A frontside surface of the first backside dielectric fill extends a second width along the y-axis. The second width is greater than the first width.