Dual-Side Exposed Semiconductor Package for Low Resistance and Heat Dissipation
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Solution Overview
Problem
Semiconductor wafers thinner than 200 microns are prone to cracking during grinding and packaging, which hinders the development of semiconductor packages with low resistance and high heat dissipation in power MOSFET applications.
Innovation Solution
A dual-side exposed semiconductor package with an ultra-thin die is manufactured by grinding the wafer to 300-400 microns, forming Ni/Au or Cu pillars, and using a titanium-nickel-silver alloy back metal layer, along with a method involving multiple molding compounds and metal clips to expose terminals and enhance heat dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the semiconductor wafer is ground to below 200 microns to reduce device resistance, then the resistance performance is improved, but the wafer is likely to be cracked during grinding and subsequent cutting and packaging process
Solution Approach 1:
The wafer is ground to a intermediate thickness of 300-400 microns before die attachment, rather than grinding to the final ultra-thin dimension. This preliminary grinding stage prevents cracking during subsequent handling and packaging operations, while the ultra-thin die structure is still achieved in the final product through the thinning of individual dies after attachment to the lead frame
Solution Approach 2:
The molding compound is deposited to a thickness of 450-500 microns before grinding, providing a cushioning layer that supports the ultra-thin die during the grinding process. This cushioning prevents the die from cracking while being ground to the final thickness, as the molding compound absorbs mechanical stresses
2Manufacturing precision
If the wafer is ground to ultra-thin dimensions to improve resistance, then the electrical performance is improved, but the thermal performance and heat dissipation are compromised
Solution Approach 1:
The invention transitions from single-side exposure to dual-side exposure of terminals, utilizing both the top and bottom surfaces of the package for electrical connections and heat dissipation. This dimensional change allows heat to be dissipated through multiple pathways, compensating for the reduced thermal mass of the ultra-thin die
Solution Approach 2:
The package employs composite material structures including the titanium-nickel-silver alloy back metal layer (20 microns thick) combined with the molding compound and lead frame. These composite materials provide enhanced thermal conductivity and heat dissipation capabilities while maintaining the ultra-thin die structure for low resistance
3Temperature
If the molding compound thickness is reduced to expose the back surface of the die, then the heat dissipation is improved, but the mechanical protection and structural integrity are reduced
Solution Approach 1:
The molding compound thickness is precisely controlled and thinned to a specific range (equal to or less than 50 microns, matching the total thickness of the thinned die and metal layers). This parameter optimization allows sufficient heat dissipation while maintaining adequate mechanical protection. The precise control of thickness parameters ensures both thermal performance and structural integrity are achieved
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution results in improved heat dissipation and reduced device resistance by exposing the source, gate, and drain terminals, while preventing wafer cracking through controlled grinding and molding compound support.
Implementation Method 1
grinding from the back surface of the wafer to a thickness of about 300 microns to 400 microns
Implementation Method 2
forming the source electrode and the gate electrode at the top surface of each die with Ni/Au electroplating or Cu pillars
Implementation Method 3
depositing a first molding compound on the top surface of the lead frame fully covering the flipped die attached to the lead frame
Implementation Method 4
grinding the top surface of the first molding compound and the back surface of the flipped die to thin the molding compound and the die and to expose the back surface of the flipped die
Implementation Method 5
depositing a back metal layer at the exposed area of the back surface of the flipped die, the metal layer is electrically connected to the drain region at the back of the die forming the drain electrode of the die
Data Source
AI summary
A dual-side exposed semiconductor package with ultra-thin die and a manufacturing method are disclosed. A die having a source electrode and a gate electrode at top surface is flipped and attached to a die paddle of a lead frame and then is encapsulated with a first molding compound. The first molding compound and the die are ground to reduce the thickness. A mask is applied atop the lead frame with the back of the flipped die exposed and a metal layer is deposited on the exposed area at the back of the flipped die. A metal clip is attached to the back of the flipped die. A second molding compound is deposited on the lead frame with the top surface of the metal clip exposed from the top surface of the second molding compound and the bottom surface of the lead frame exposed from the bottom surface of the second plastic molding compound.