Dual-Side Gate Pad MOSFET for Parasitic Inductance Reduction

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Solution Overview

Problem

Power MOSFET devices face efficiency losses and electromagnetic interference (EMI) issues due to parasitic inductance and traditional packaging limitations, especially in high-frequency and high-current applications, where the existing solutions either increase costs or are not adaptable to different mounting orientations.

Innovation Solution

The MOSFET device is designed with a gate pad on each main side of the die, allowing for flexible mounting with either the drain or source pad facing the leadframe, enabling reduced parasitic inductance and EMI by ensuring one gate metallization is accessible for wire-bonding, thus allowing for adaptable packaging and reduced costs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Object-affected harmful factors

If traditional packaging with single-side gate pad is used, then manufacturing simplicity is maintained, but parasitic inductance increases and EMI performance deteriorates

Engineering Contradiction:
Improveparasitic inductanceVSAvoidgate pad configuration
Core Design Contradiction:
Object-affected harmful factorsVSDevice complexity

Solution Approach 1:

The gate pad function is segmented into two separate locations: a first gate pad on the front surface and a second gate pad on the rear surface of the die. This segmentation allows independent optimization of each gate pad's function, enabling reduced parasitic inductance paths while maintaining manufacturing simplicity through standardized processes.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The gate pad configuration transitions from a two-dimensional single-side arrangement to a three-dimensional dual-side arrangement. By placing gate pads on both the front and rear surfaces of the die, the invention creates additional electrical pathways that reduce parasitic inductance without significantly increasing manufacturing complexity.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Adaptability or versatility

If flexible mounting orientation is enabled, then adaptability improves, but manufacturing complexity increases

Engineering Contradiction:
Improvemounting orientation flexibilityVSAvoidpackaging configuration
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The MOSFET die is designed with universal functionality for both front-side and rear-side mounting orientations. The dual gate pad configuration and symmetric drain/source pad arrangement enable the same die to be mounted in either orientation without requiring different die designs, achieving multi-functionality that improves adaptability while keeping manufacturing straightforward.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The invention enables mounting orientation inversion by providing functional equivalence for both front-side and rear-side attachment. The second gate pad on the rear surface specifically enables the die to be mounted with the rear surface facing the leadframe, inverting the traditional mounting orientation while maintaining all electrical functions.

Inventive Principle:
Principle #13The other way round (Inversion)

3Object-generated harmful factors

If dual gate pads are implemented, then EMI is reduced and efficiency improves, but manufacturing precision requirements increase

Engineering Contradiction:
Improveelectromagnetic interferenceVSAvoidpad alignment precision
Core Design Contradiction:
Object-generated harmful factorsVSManufacturing precision

Solution Approach 1:

The gate pad structures are pre-configured during die fabrication with precise geometric relationships established in advance. The first and second gate pads are formed with predetermined positions, sizes, and orientations that ensure proper alignment with corresponding pads on the leadframe, eliminating the need for high-precision alignment during assembly.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The invention optimizes geometric parameters of the gate pads, including their dimensions, spacing, and positional relationships, to achieve effective EMI reduction while maintaining tolerance margins that accommodate normal manufacturing variations. The pad parameters are designed to be robust against typical manufacturing tolerances.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS10770576B2Power MOSFET device and manufacturing process thereof
Publication Date: 2020.09.08 STMICROELECTRONICS SRL
  • US10770576B2 patent drawing
  • US10770576B2 patent drawing
  • US10770576B2 patent drawing

AI summary

A MOSFET device is integrated in a body of semiconductor material of a first conductivity type accommodating a body region, of a second conductivity type, and a source region, of the first conductivity type. A gate region extends over the top surface of the body; a source pad extends over the first top surface and is electrically coupled to the source region, a first gate pad extends over the first main surface, alongside the source pad, and is electrically coupled to the gate region; a drain pad extends over the rear surface and is electrically coupled to the body; a second gate pad extends over the rear surface, alongside the drain pad; and a conductive via extends through the body and electrically couples the gate region to the second gate pad.