Dual-Side IC Structure Annealing Without BEOL Damage
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Monolithic 3D integrated circuit structures face challenges in activating active devices on semiconductor layers without damaging back-end-of-line (BEOL) and far BEOL copper interconnects, as high-temperature anneals required for activation can damage these structures, necessitating costly and time-consuming shield layers.
Innovation Solution
The use of a single semiconductor substrate with active devices on both sides allows for annealing without damaging BEOL interconnects, as the anneals can exceed temperatures that would normally damage these structures, eliminating the need for shielding layers by forming active devices on both sides of the substrate and electrically coupling them through through-silicon vias (TSVs).
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-temperature anneals are performed to activate active devices on semiconductor layers, then device activation is achieved, but BEOL and FBEOL copper interconnect structures are damaged
Solution Approach 1:
The patent transitions from a planar monolithic 3D structure to a vertically stacked 3D structure where active devices are formed on both the front and back surfaces of the semiconductor substrate. This dimensional change allows high-temperature annealing to be performed without damaging BEOL interconnects, as the interconnect structures can be formed after the annealing process or protected by the substrate itself, thereby resolving the contradiction between achieving device activation and preventing interconnect damage
Solution Approach 2:
The patent performs high-temperature annealing to activate active devices before forming the BEOL and FBEOL copper interconnect structures. By completing the device activation process beforehand, the subsequent interconnect formation occurs at lower temperatures that do not damage the already-activated devices, thus eliminating the need for shield layers and resolving the contradiction
2Object-affected harmful factors
If shield layers are used to protect interconnect layers during annealing, then interconnect structures are protected from damage, but manufacturing costs and process time increase
Solution Approach 1:
The patent removes the shield layers from the manufacturing process by changing the sequence of operations. Instead of using shield layers to protect interconnects during annealing, the process extracts the annealing step and performs it before interconnect formation, or performs it on the opposite surface of the substrate where no interconnects are present, thereby simplifying the manufacturing process and reducing costs
3Productivity
If monolithic 3D structures with multiple semiconductor layers are used, then circuit density increases, but the number of layers and process complexity increase
Solution Approach 1:
The patent achieves increased circuit density by utilizing both the front and back surfaces of a single semiconductor substrate, effectively doubling the available area for active devices without stacking multiple semiconductor layers. This approach maintains lower process complexity while achieving high circuit density through vertical stacking of interconnect layers and through-silicon vias
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the number of semiconductor layers, saves costs and process time, and enables smaller chip footprints with increased functional volume, allowing for faster devices and reduced thermal cooling issues by enabling load sharing of logic cores across both sides of the substrate without damaging BEOL interconnects.
Implementation Method 1
anneals are performed to activate the devices, e.g., to diffuse dopants on the semiconductor layers
Implementation Method 2
anneals necessary to activate active devices in the various semiconductor layers
Data Source
AI summary
An integrated circuit (IC) structure uses a single semiconductor substrate having a first side and an opposing, second side. A first plurality of active devices are positioned on the first side of the single semiconductor substrate, and a second plurality of active devices are positioned on the opposing, second side of the single semiconductor substrate. A TSV may electrically couple active devices on either side. Use of a single semiconductor substrate with active devices on both sides reduces the number of semiconductor layers used and allows annealing without damaging BEOL interconnects during fabrication.