Dual-Side Logic Circuit Block Layouts for RF Transceiver Area Savings
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Solution Overview
Problem
Conventional CMOS transistor fabrication is limited to one side of a semiconductor wafer, leading to design complexity and reduced transistor density in mobile RF transceivers, particularly at deep sub-micron process nodes, which complicates the integration of dual-sided processing and increases parasitic capacitance.
Innovation Solution
The integration of p-type and n-type metal oxide semiconductor transistors on opposite sides of an isolation layer, with shared contacts for electrical coupling, enabling dual-sided processing and reducing parasitic capacitance through a post-layer transfer process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional one-sided CMOS transistor fabrication is used, then manufacturing simplicity is maintained, but transistor density and circuit area efficiency deteriorate
Solution Approach 1:
The patent transitions from single-sided to dual-sided transistor fabrication by utilizing both front and back surfaces of the semiconductor wafer. Front-side NMOS transistors and back-side PMOS transistors are fabricated simultaneously, effectively adding a spatial dimension to the manufacturing process. This doubles the transistor density without increasing the wafer footprint, directly resolving the contradiction between manufacturing simplicity and transistor density.
2Area of moving object
If dual-sided processing is implemented, then transistor density and area efficiency improve, but processing complexity increases
Solution Approach 1:
The patent segments the CMOS fabrication process into independent front-side and back-side operations. NMOS transistors are fabricated on the front side while PMOS transistors are fabricated on the back side using separate processing streams. This segmentation allows each side to be processed independently with optimized procedures, reducing the overall processing complexity despite the dual-sided approach.
Solution Approach 2:
The patent employs preliminary actions by forming isolation structures, doping regions, and patterning layers on each side before final assembly. Handle substrates are attached and prepared in advance, and sacrificial layers are pre-formed to facilitate subsequent processing steps. These preliminary actions streamline the dual-sided fabrication process and reduce complexity.
3Ease of manufacture
If SOI technology with reduced BOX layer thickness is used, then manufacturing cost is reduced, but parasitic capacitance increases
Solution Approach 1:
The patent utilizes the vertical dimension by attaching handle substrates to the front side of the SOI structure, positioning them close to the active devices. This three-dimensional configuration reduces the effective distance between signal paths and reference planes, thereby reducing parasitic capacitance without increasing the horizontal footprint or manufacturing complexity.
Solution Approach 2:
The patent applies local quality by implementing asymmetric doping profiles and selective isolation structures on the back side of the SOI layer. The PMOS transistors are doped and isolated differently from the front-side NMOS transistors, optimizing each region's electrical characteristics to minimize parasitic effects while maintaining cost-effective manufacturing.
4Ease of manufacture
If logic circuit blocks are laid out conventionally on one side, then manufacturing simplicity is maintained, but logic gate area efficiency deteriorates
Solution Approach 1:
The patent implements dual-sided logic gate layouts where complementary logic functions are distributed across front and back surfaces. AND gates on the front side are paired with OR gates on the back side, sharing common input/output contacts. This three-dimensional logic block arrangement reduces the area required for each logic function by approximately 60% compared to conventional planar layouts, while maintaining manufacturing simplicity through standardized fabrication processes.
Data Source
AI summary
An integrated circuit device may include a p-type metal oxide semiconductor (PMOS) transistor supported by a backside of an isolation layer. The integrated circuit device may also include an n-type metal oxide semiconductor (NMOS) transistor supported by a front-side of the isolation layer, opposite the backside. The integrated circuit device may further include a shared contact extending through the isolation layer and electrically coupling a first terminal of the PMOS transistor to the first terminal of the NMOS transistor.