Dual-Side Metallization Layout for Semiconductor Routing Bottlenecks
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Solution Overview
Problem
The semiconductor industry faces a paucity of routing resources due to reduced component sizes and tightened spacing, leading to inefficiencies in metallization layer usage, particularly with EUV lithography being more expensive and less efficient than 193i lithography.
Innovation Solution
Utilizing back side BM_first routing segments to supplement front side M_first routing segments, employing 193i lithography to produce taller BM_first routing segments, reducing the need for EUV lithographic masks, and optimizing cell region layouts to enhance routing efficiency and reduce costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If component sizes are reduced and spacing is tightened to increase transistor density, then device integration is improved, but routing resources become insufficient
Solution Approach 1:
The patent utilizes the back side of the semiconductor device as an additional dimension for routing. By forming BM_first routing segments on the back side that correspond to front side M_first routing segments, the invention effectively doubles the available routing resources without increasing the footprint or transistor density requirements. This dimensional approach resolves the contradiction by providing more routing capacity while maintaining high device integration.
2Manufacturing precision
If EUV lithography is used to produce routing segments, then routing precision is improved, but manufacturing cost increases
Solution Approach 1:
The patent segments the routing segment formation process into two distinct parts: front side M_first routing segments formed by 193i lithography and back side BM_first routing segments formed by EUV lithography. This segmentation allows the expensive EUV process to be used only where absolutely necessary (back side segments), while the majority of routing (front side segments) is produced by the cheaper 193i process, thereby reducing overall manufacturing cost while maintaining routing precision.
Solution Approach 2:
The back side BM_first routing segments are designed to correspond to and supplement the front side M第一 routing segments. By creating these corresponding routing segments on the back side, the invention effectively copies the routing architecture to an additional layer, thereby increasing routing capacity without requiring all segments to be formed by the expensive EUV process.
3Ease of manufacture
If 193i lithography is used to produce routing segments, then manufacturing cost is reduced, but routing resource capacity is insufficient
Solution Approach 1:
The patent employs the back side of the device as an additional dimension to supplement routing resources. By forming BM_first routing segments on the back side that correspond to front side M_first routing segments, the invention increases total routing capacity while keeping the primary routing segments formed by cost-effective 193i lithography.
4Ease of manufacture
If taller BM_first routing segments are produced using 193i lithography, then manufacturing cost is reduced, but routing efficiency may be compromised
Solution Approach 1:
The patent changes the height parameter of the BM_first routing segments by producing them as taller structures using 193i lithography. These taller segments provide sufficient vertical connectivity while being manufactured at lower cost. The height parameter adjustment allows the less precise 193i lithography process to achieve the required routing function without compromising efficiency.
Data Source
AI summary
A device includes: a first cell region stacked on a second cell region; each including a first active region over a second active region; in a first layer of metallization (M_first layer) over the first active region, M_first power grid (PG) segments having a first reference voltage and M_first routing segments aligned correspondingly to M_first routing tracks; and in a first layer of metallization (BM_first layer) under the second active region, BM_first PG segments having a second reference, and BM_first routing segments aligned correspondingly to BM_first routing tracks. The M_first routing segments are aligned in the first and second cell regions correspondingly to first (Q1) and second (Q2) quantities of the M_first routing tracks, where Q2<Q1. The BM_first routing segments are aligned in the first and second cell regions correspondingly to third and fourth quantities of the BM_first routing tracks, where Q4<Q3.


