Dual-Side Molded Package Substrate for Heat Dissipation and Warpage
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Solution Overview
Problem
Transitioning FCBGA packages from Ajinomoto build-up film (ABF) to prepreg dielectric materials for larger body sizes presents assembly manufacturing yield and thermal performance challenges, including warpage and insufficient thermal dissipation in conventional FCCSP solutions.
Innovation Solution
A dual side molded package substrate with no solder mask, featuring first and second molded package structures made of high thermal conductivity epoxy molding compound, attached to a multilevel package substrate with semiconductor die, providing improved thermal performance and reduced warpage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If FCBGA packages transition from ABF to prepreg dielectric materials for larger body sizes, then manufacturing cost is reduced, but thermal performance deteriorates
Solution Approach 1:
The patent uses a composite material structure combining prepreg dielectric layers with high thermal conductivity epoxy molding compound (EMC) having thermal conductivity of 3-10 W/mK. This composite approach allows the package to maintain the cost benefits of prepreg materials while incorporating thermally conductive EMC to improve heat dissipation performance, thereby resolving the contradiction between manufacturing cost and thermal performance.
2Ease of manufacture
If conventional FCCSP solutions are used for larger body sizes, then cost is reduced, but warpage increases during manufacturing
Solution Approach 1:
The patent changes the material parameters by selecting prepreg dielectric materials and epoxy molding compounds with matched thermal expansion coefficients and controlled moisture content. This parameter optimization reduces differential stress during temperature cycling and manufacturing processes, thereby minimizing substrate warpage while maintaining the cost advantages of prepreg-based FCCSP structures.
3Temperature
If ABF substrate material is used for larger body sizes, then thermal performance is maintained, but manufacturing cost increases
Solution Approach 1:
The patent applies local quality by using standard cost-effective prepreg dielectric materials for the substrate layers while concentrating high thermal conductivity EMC specifically in the molded package structures that directly contact and encapsulate the semiconductor die. This localized application of high-performance thermal material maximizes heat dissipation where it is most needed while minimizing overall material costs.
4Ease of manufacture
If solder mask is applied to package substrate, then manufacturing process is complete, but additional processing steps and cost are added
Solution Approach 1:
The patent merges the functions of the molding compound and traditional solder mask by using the epoxy molding compound to provide both package encapsulation and surface protection functions. The EMC is applied during the molding process to form a continuous protective layer over the conductive features, eliminating the need for separate solder mask application, patterning, and curing steps, thereby reducing device complexity and processing steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances thermal conductivity by 1.8-8.4%, reduces substrate warpage by up to 85%, and lowers manufacturing costs by eliminating solder mask processing steps, while maintaining high I/O density interconnection.
Implementation Method 1
a first molded package structure on the first side and a second molded package structure on the second side and spaced apart from the first molded package structure
Data Source
AI summary
An electronic device includes a multilevel package substrate having opposite first and second sides, a semiconductor die attached to the first side, a first molded package structure on the first side, and a second molded package structure on the second side and spaced apart from the first molded package structure. A method of fabricating an electronic device includes attaching a semiconductor die to a first side of a soldermaskless multilevel package substrate, forming a first molded package structure on the first side of the multilevel package substrate, and forming a second molded package structure on an opposite second side of the multilevel package substrate and spaced apart from the first molded package structure.


