Dual Side Package on Package for Reduced Metallization and Thermal Management
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Solution Overview
Problem
The complexity of electrical connections between signal processing and memory chips on circuit boards, requiring multiple metallization levels and via-comprising bridges, complicates manufacturing and increases costs, while also posing challenges in heat dissipation and signal routing.
Innovation Solution
An electronic package design featuring a substrate wafer with an interconnect network, where one chip is mounted on the front side and connected via wires, and another on the back side, with peripheral front-side electrical connection elements extending beyond an encapsulating body, allowing for reduced metallization levels on the circuit board and improved heat dissipation using a thermally conductive material.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple memory chips are connected to a signal processing chip on a circuit board, then the required memory capacity is achieved, but the number of metallization levels and via-comprising bridges must be increased, complicating manufacturing and increasing costs
Solution Approach 1:
The patent transitions from a planar 2D connection architecture to a 3D stacked architecture. Memory chips are vertically stacked above the signal processing chip, utilizing the third dimension (height) for interconnection. This allows multiple memory chips to be connected without proportionally increasing the number of metallization levels on the circuit board, as connections are established through vertical vias and wire bonds within the stack rather than through multiple board-level metallization layers.
Solution Approach 2:
The patent introduces an intermediary substrate or carrier that holds the signal processing chip and provides connection points for both the memory chips and the circuit board. This intermediary structure acts as a mediator, consolidating multiple connections into fewer external connection points on the circuit board, thereby reducing the complexity of the electrical connection network at the board level.
2Reliability
If multiple metallization levels and via-comprising bridges are used to connect memory chips to signal processing chips, then the required electrical connections are established, but manufacturing difficulty and production costs increase
Solution Approach 1:
The patent segments the electrical connection system into distinct modules: the circuit board, the intermediary substrate, and the chip stack. Each module can be manufactured and tested independently, with connections established through standardized interfaces. This segmentation allows for simpler individual manufacturing processes compared to creating a single complex multi-level metallization structure on the circuit board itself.
Solution Approach 2:
By moving connections into the vertical dimension through stacked chips and vertical vias, the patent reduces the need for multiple horizontal metallization levels on the circuit board. This dimensional transition simplifies the circuit board manufacturing process while maintaining reliable electrical connections through the vertical interconnect structure.
3Speed
If numerous electrical connections are made between memory chips and signal processing chips on a circuit board, then the required data transfer capacity is achieved, but routing constraints related to signal frequency, differential pairs, impedance control, and connection length become more difficult to satisfy
Solution Approach 1:
The intermediary substrate serves as a mediator that provides controlled impedance paths and standardized connection interfaces between the memory chips and signal processing chip. This intermediary structure allows for systematic management of routing constraints, as connections are established through predefined via locations and trace patterns on the intermediary substrate rather than requiring complex direct routing between chips on the circuit board.
Solution Approach 2:
The vertical stacking architecture reduces the horizontal distance between memory chips and the signal processing chip, thereby reducing connection length and associated routing constraints. The vertical vias provide direct, short connection paths that are easier to control for impedance and signal integrity compared to long, complex horizontal traces on a multi-level circuit board.
4Quantity of substance
If multiple memory chips are mounted on a circuit board near signal processing chips, then the required memory capacity is achieved, but heat dissipation becomes more difficult
Solution Approach 1:
By stacking memory chips vertically above the signal processing chip, the patent distributes heat-generating components in the vertical dimension rather than concentrating them in a planar arrangement on the circuit board. This vertical distribution allows for better thermal management, as heat can be dissipated through multiple surfaces (top and bottom of each chip) and through the vertical interconnect structure, reducing thermal accumulation in any single location.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design simplifies the manufacturing process, reduces costs, and effectively manages high-frequency signal constraints and heat dissipation by allowing fewer metallization levels on the circuit board and enhanced thermal management.
Implementation Method 1
a thermally conductive material is interposed between the encapsulating body and the circuit board
Data Source
AI summary
An electronic package includes a substrate wafer with an interconnect network. A first chip is fixed to a front of the substrate, connected to the interconnect network and encapsulated by a body. A second chip is placed on a back side of the substrate wafer and connected to the interconnect network by back-side connection elements interposed between the back side of the substrate and a front side of the second chip. Front-side connection elements are placed on the front side of the substrate and connected to the interconnect network. The connection elements extend beyond the frontal face of the body. The package may be mounted on a board with an interposed thermally conductive material.