Dual-Side Power Rail Layout for Front-Side Chip Testing
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Solution Overview
Problem
As semiconductor devices continue to integrate more components into a given area through reduced minimum feature sizes, challenges arise in efficiently forming and testing power delivery networks and input/output pins, which affect the performance and reliability of semiconductor devices.
Innovation Solution
The implementation of dual-side power rail (SPR) in semiconductor devices, where power delivery networks and I/O pins are included on both the front and back sides, allowing for separate testing through the front side without blocking physical failure analysis, and enabling chip tests on the front side when needed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If power delivery networks and I/O pins are formed only on the back side of the semiconductor device, then area is saved and resistance is reduced, but testing and physical failure analysis are blocked
Solution Approach 1:
The patent extends the power delivery network from a single-plane (back side only) configuration to a multi-dimensional configuration by adding front-side power rails. This allows testing and analysis to occur on the front side while maintaining the back-side power delivery network, effectively using both sides of the device to resolve the contradiction between testing accessibility and area efficiency.
Solution Approach 2:
The power delivery network is segmented into separate front-side and back-side components. The back side contains the primary power delivery network with power rails and I/O pins, while the front side contains additional power rails that can be used for testing and analysis without interfering with the back-side functionality. This segmentation allows each side to serve specialized functions.
2Quantity of substance
If minimum feature sizes are reduced to increase integration density, then more components can be integrated into a given area, but manufacturing precision and reliability of power delivery networks deteriorate
Solution Approach 1:
Instead of further reducing feature sizes to increase integration density, the patent adds another dimension by utilizing the front side of the device for additional power rails. This approach increases the effective area available for power delivery without requiring smaller features, thereby maintaining manufacturing precision while achieving higher integration density.
3Reliability
If scanning beams are used for physical failure analysis on the front side, then defect detection is enabled, but the beams are blocked by existing structures
Solution Approach 1:
The patent extracts or removes certain structures from the front side that would block scanning beams during physical failure analysis. By selectively positioning or removing blocking structures, the front side becomes accessible to scanning beams while still maintaining the necessary power delivery functionality through the added power rails.
Data Source
AI summary
Methods of forming dual-side super power rails in semiconductor devices, semiconductor devices including the same, and methods of testing the semiconductor devices are disclosed. In an embodiment, a device includes a transistor structure; a front-side interconnect structure on a front side of the transistor structure; and a back-side interconnect structure on a back side of the transistor structure. The front-side interconnect structure includes a front-side power delivery network (PDN) and a front-side input/output (I/O) pin. The back-side interconnect structure includes a back-side PDN.