Dual-Side Gate Stages for Scan Output Detection
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Solution Overview
Problem
Display devices with NSDC-type stages experience output characteristic deviations in scan signals due to varying Q node voltages at rising and falling edges, leading to charge deviations between pixel lines.
Innovation Solution
Implement a sensing driving mode (SDM) where first-side and second-side stages operate in alternate modes to detect and compensate for output characteristic deviations by using first and second output and sensing circuits, adjusting delays and slew rates of scan clocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If NSDC-type stages are used to decrease gate driver design area, then device area is reduced, but output characteristic deviation occurs between scan signals
Solution Approach 1:
The gate driver is divided into first-side and second-side stages that operate independently but symmetrically. Each stage has its own output and sensing circuit, allowing independent detection and compensation of output characteristics. This segmentation enables the system to maintain compact design while achieving precise output control through localized optimization of each stage.
Solution Approach 2:
The sensing circuit detects the actual output characteristic of the scan signal from each stage and feeds this information back to the control circuit. Based on the detected deviation, the control circuit adjusts the drive signals to compensate for output characteristic variations. This feedback mechanism ensures consistent scan signal output while maintaining the compact NSDC-type architecture.
2Productivity
If Q node voltage varies at rising and falling edges of scan clocks, then scan signals are generated, but output characteristic deviation occurs
Solution Approach 1:
The sensing circuit performs preliminary detection of the Q node voltage and output characteristic before the scan signal is fully generated. By detecting the deviation early in the process, the control circuit can pre-adjust the drive signals to compensate for expected output variations, ensuring consistent scan signal output despite Q node voltage fluctuations.
Solution Approach 2:
The control circuit dynamically adjusts drive signal parameters (voltage levels, timing) based on the detected Q node voltage and output characteristic. When deviation is detected, the control circuit modifies the drive parameters to compensate for the Q node voltage variation, maintaining consistent scan signal output across different operating conditions.
3Manufacturing precision
If scan signal output is detected to compensate for deviation, then output characteristic consistency is improved, but detection complexity increases
Solution Approach 1:
The sensing circuit is designed to perform multiple functions: it detects the Q node voltage, measures the output characteristic of the scan signal, and provides feedback for compensation. By making the sensing circuit multi-functional, the patent avoids adding separate dedicated detection components, thereby limiting the increase in device complexity while achieving precise output characteristic detection.
Solution Approach 2:
The sensing circuit is integrated with the existing gate driver structure, merging the detection function with the signal generation function. The sensing circuit shares the same Q node and scan signal paths as the main driver circuit, combining detection and drive operations into a unified system. This integration minimizes additional complexity while enabling accurate output characteristic detection.
Data Source
AI summary
A display device includes a first-side stage that supplies a first-side scan signal to a first side of a gate line, a second-side stage that supplies a second-side scan signal having the same phase as the first-side scan signal to a second side of the gate line, a first output and sensing circuit connected to the first-side stage through a first clock line, and a second output and sensing circuit connected to the second-side stage through a second clock line, wherein the first-side stage operates in an output mode and the second-side stage operates in a bypass mode to detect an output characteristic of the first-side scan signal in the second output and sensing circuit, and the second-side stage operates in the output mode and the first-side stage operates in the bypass mode to detect an output characteristic of the second-side scan signal in the first output and sensing circuit.