Dual-Side S/D Via Structure for Lower Contact Resistance
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Solution Overview
Problem
As integrated circuits (ICs) become more compact with smaller feature sizes and higher device density, challenges arise in the fabrication processes, particularly with conductive vias placed in device regions between conductive peripherals. The contact area between metal lines and conductive vias affects resistance, leading to higher resistance issues due to smaller contact areas or misalignment.
Innovation Solution
Connecting a conductive via with an adjacent source/drain (S/D) region using both front-side and back-side contact structures increases the contact area, reducing via resistance and improving device performance. This is achieved by extending the conductive via between layers and using epitaxially grown semiconductor materials for enhanced back-side connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If IC features are scaled down to increase device density, then device capacity increases, but contact area between metal lines and conductive vias decreases leading to higher resistance
Solution Approach 1:
The patent extends the conductive via from a single-plane structure to a three-dimensional structure by adding back-side connections through the substrate. This dimensional extension allows the via to connect to the S/D region from multiple directions (front-side and back-side), effectively increasing the total contact area without occupying additional lateral space, thus resolving the contradiction between high device density and low via resistance.
Solution Approach 2:
The patent implements a nested structure where the conductive via is positioned within the device region and connects to the S/D region through multiple levels. The via structure is nested within the substrate thickness, with front-side and back-side contact structures arranged at different vertical levels, maximizing space utilization while increasing contact area.
2Length of moving object
If contact area between metal lines and conductive vias is reduced for scaling, then feature size decreases, but manufacturing precision requirements increase due to misalignment risks
Solution Approach 1:
By transitioning from a two-dimensional contact interface to a three-dimensional multi-level contact structure, the patent distributes the alignment requirement across multiple contact points (front-side and back-side) rather than relying on a single critical interface. This reduces the impact of misalignment at any single interface while maintaining small feature sizes.
Solution Approach 2:
The patent applies different contact configurations at different locations: front-side contact structures at the top surface and back-side contact structures at the bottom surface. This localized differentiation allows each contact interface to be optimized independently, reducing the cumulative effect of alignment variations across the structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The increased contact area between the conductive via and the S/D region reduces resistance in the conductive via, leading to improved device performance and yield by filling gaps caused by defects or process side effects.
Implementation Method 1
using epitaxially grown semiconductor materials for enhanced back-side connections
Data Source
AI summary
A fabrication method and associated integrated circuit (IC) structures and devices that include a conductive via with front-side and back-side connections with an S/D region are described herein. In one example, an IC structure includes a conductive via extending between a first layer and a second layer and an S/D region of a transistor between the first layer and the second layer, where the S/D region includes a first semiconductor material and a second semiconductor material. In one such example, the second semiconductor material may be epitaxially grown on the first semiconductor material of the S/D region from a back side of the IC structure. Conductive elements in layers over and under the conductive via may couple the conductive via with the S/D region from both the front-side and back-side S/D contact structures.