Dual-Side Semiconductor Devices on Isolation Layer
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Solution Overview
Problem
The design of mobile RF transceivers in deep sub-micron process nodes faces complexity due to added circuit functions for communication enhancements, and silicon on insulator (SOI) technology limitations, such as reduced parasitic capacitance and hydrogen implantation requirements, which complicate the formation of CMOS transistors on both sides of a buried oxide (BOX) layer.
Innovation Solution
The integration of front-side and backside transistors on opposite sides of an isolation layer with shared contacts, allowing for the formation of semiconductor devices on both sides of the BOX layer without hydrogen implantation, using a handle substrate and etch stop or enhancement layers to facilitate layer transfer and device formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If SOI technology is used to reduce parasitic capacitance, then device performance is improved, but manufacturing complexity increases due to hydrogen implantation requirements
Solution Approach 1:
The patent extracts and removes the hydrogen implantation step from the SOI fabrication process. By forming transistors on both sides of the BOX layer without requiring hydrogen implantation, the invention eliminates this complex manufacturing step while maintaining the parasitic capacitance reduction benefits of SOI technology
Solution Approach 2:
The patent inverts the conventional approach by forming transistors on both sides of the BOX layer simultaneously rather than sequentially. This bidirectional formation approach eliminates the need for hydrogen implantation and reduces manufacturing complexity while maintaining device performance
2Adaptability or versatility
If transistors are formed on both sides of BOX layer, then device integration is enhanced, but process complexity increases due to additional masks and steps
Solution Approach 1:
The patent merges the transistor formation processes for both sides of the BOX layer into a unified process flow. By combining the formation steps and eliminating redundant masks and processes, the invention achieves enhanced device integration without proportionally increasing process complexity
Solution Approach 2:
The patent creates a universal fabrication process that forms transistors on both sides of the BOX layer using the same process steps. This multi-functional approach allows a single process sequence to achieve dual-sided transistor formation, reducing the need for additional specialized masks and process variations
3Ease of manufacture
If conventional FEOL processes are used, then CMOS transistors can be formed, but only on one side of the semiconductor wafer
Solution Approach 1:
The patent extends the conventional single-sided FEOL process into the third dimension by forming transistors on both sides of the BOX layer. This dimensional expansion utilizes the full thickness of the wafer, effectively doubling the active device area without requiring additional wafer layers or complex 3D stacking
Data Source
AI summary
An integrated circuit device includes only semiconductor devices with a same first polarity on one side of an insulator layer and only semiconductor devices with a different second polarity on an opposite side of the insulator layer to reduce size and complexity of the integrated circuit device as well as reducing the process steps associated with fabricating the integrated circuit device. Shared contacts between backside source/drain regions or spacers of the semiconductor devices with the first polarity and front-side source/drain regions or spacers of the semiconductor devices with the first polarity are used to connect the semiconductor devices on opposite sides of the insulator layer.