Dual-Side Semiconductor Interconnects with Passthrough Vias
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Solution Overview
Problem
As semiconductor devices continue to scale down, the increasing number of devices on integrated circuit chips requires more complex and dense interconnect wiring, which is challenging to achieve with conventional front-end-of-line (FEOL) and back-end-of-line (BEOL) processing, particularly due to the limitations of metal layer additions and routing resources on a single side of the chip.
Innovation Solution
The technique involves forming interconnects on both sides of a semiconductor structure with passthrough vias that connect interconnects between the front-end-of-line (FEOL) and back-end-of-line (BEOL) regions, allowing for additional routing resources and enabling vertical three-dimensional stacked devices by leveraging both sides of the FEOL region for increased wiring density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional single-sided interconnect wiring is used, then manufacturing process is simpler, but routing resources are insufficient for increased device density
Solution Approach 1:
The patent transitions from conventional single-sided (2D planar) interconnect wiring to dual-sided (3D volumetric) interconnect wiring by forming interconnect structures on both the front and back sides of the semiconductor substrate. This dimensional expansion effectively doubles the available routing resources without increasing the footprint area, directly resolving the contradiction between routing resource quantity and structural complexity.
2Quantity of substance
If more metal layers are added to increase routing capacity, then routing resources increase, but manufacturing complexity and cost increase
Solution Approach 1:
Instead of adding more metal layers in the vertical direction on a single side, the patent utilizes the third dimension by extending interconnect routing to both sides of the substrate. This approach increases routing capacity by leveraging the back side of the chip, avoiding the need for additional fabrication steps associated with adding more metal layers.
Solution Approach 2:
The interconnect structure is segmented into front-side interconnects and back-side interconnects, with passthrough vias serving as connection points between the two segments. This segmentation allows each side to be manufactured and optimized independently, then combined through the passthrough via formation process, thereby increasing routing resources while managing manufacturing complexity.
3Productivity
If device density is increased, then chip performance improves, but interconnect routing becomes more challenging
Solution Approach 1:
By transitioning to dual-sided interconnect wiring, the patent effectively increases the available routing space proportionally to the increased device density. The back side of the substrate provides additional routing channels that can handle the increased interconnect demands from higher device density, thus resolving the contradiction between productivity and interconnect complexity.
Data Source
AI summary
A semiconductor structure comprises a front-end-of-line region comprising two or more devices, a first back-end-of-line region on a first side of the front-end-of-line region, the first back-end-of-line region comprising a first set of interconnects for at least a first subset of the two or more devices in the front-end-of-line region, and a second back-end-of-line region on a second side of the front-end-of-line region opposite the first side of the front-end-of-line region, the second back-end-of-line region comprising a second set of interconnects for at least a second subset of the two or more devices in the front-end-of-line region. The semiconductor structure also comprises one or more passthrough vias disposed in the front-end-of-line region, each of the one or more passthrough vias connecting at least one of the first set of interconnects of the first back-end-of-line region to at least one of the second set of interconnects of the second back-end-of-line region.