Dual-Side Shift Register Layout for Narrow Outer Frame LCD
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Solution Overview
Problem
In high-resolution liquid crystal display panels, the limited layout height of shift registers restricts the layout width, making it difficult to accommodate all components and traces within the narrow outer frame, especially as the number of pixels increases.
Innovation Solution
The implementation of two side co-used shift registers, where one shift register is disposed on each side of the pixel array, with multiple output cells coupled to each shift register to drive multiple rows of pixels, allowing for a more efficient layout and reduced required layout area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the number of pixels in the pixel array is increased to achieve high resolution, then the display resolution is improved, but the layout width of the shift register must increase which cannot be accommodated in the narrow outer frame
Solution Approach 1:
The shift register function is segmented into two separate shift registers (first shift register and second shift register) positioned on opposite sides of the pixel array. Each shift register drives a portion of the pixel rows, dividing the original single shift register's workload and reducing the required layout width for each individual shift register to fit within the narrow outer frame.
Solution Approach 2:
The shift register components are distributed from a single-sided layout to a dual-sided layout across the pixel array. By placing shift registers on both sides and using multiple output cells per side, the design transitions from a concentrated horizontal layout to a distributed bidirectional layout, effectively reducing the horizontal space requirement while maintaining the ability to drive high-resolution pixel arrays.
2Length of stationary object
If the layout height of the shift register is limited, then the outer frame width can be reduced, but the layout width of the shift register must increase which cannot be accommodated
Solution Approach 1:
The shift register system is divided into multiple independent shift registers positioned on different sides of the pixel array. Each shift register with its associated output cells forms an independent module that can be compactly laid out, allowing the overall system to fit within narrow outer frame constraints while providing sufficient driving capability for high-resolution displays.
Solution Approach 2:
Multiple output cells are combined with each shift register to drive multiple pixel rows simultaneously. This merging of output cells with their corresponding shift register creates compact functional modules that reduce the total layout area required while maintaining the ability to drive a large number of pixel rows.
3Ease of manufacture
If the layout width of the shift register is increased to accommodate components and traces, then the shift register functionality is maintained, but it cannot be accommodated in the narrow outer frame
Solution Approach 1:
The shift register components are segmented into multiple smaller shift register modules positioned on opposite sides of the pixel array. Each module contains the necessary transistors and traces for driving a portion of the pixel rows, allowing for compact local layout that fits within the narrow outer frame while maintaining complete shift register functionality across the entire display.
Solution Approach 2:
The design utilizes bidirectional placement of shift registers on both sides of the pixel array, transforming the layout from a single-directional horizontal arrangement to a distributed two-sided arrangement. This dimensional change allows components and traces to be organized in a more space-efficient manner that accommodates narrow outer frame requirements.
Data Source
AI summary
A liquid crystal display panel includes a pixel array, a first shift register, M first output cells, a second shift register, and N second output cells. The first register is disposed on a first side of the pixel array. The M first output cells are coupled to and next to the first shift register for providing M gate signals to M rows of the pixel array according to a first clock signal. The second register is disposed on a second side of the pixel array. The N second output cells are coupled to and next to the second shift register for providing N gate signals to N rows of the pixel array according to a second clock signal. M and N are positive integers.