Dual-Side Molded SiP Fine-Pitch Interconnects Without Warpage
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Solution Overview
Problem
Existing semiconductor devices face challenges with high density, fine pitch interconnects that are prone to warpage and electrical shorts, which are not adequately addressed in current manufacturing processes.
Innovation Solution
The use of conductive pillars with graphene coatings for interconnects, combined with a dual-side molded system-in-package (DSmSiP) structure, which includes conductive pillars and encapsulants to provide structural support and electrical isolation, reducing the risk of warpage and shorts while enabling high signal transmission speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If lamination is used to protect conductive posts, then protection is improved, but warpage occurs leading to defects
Solution Approach 1:
A mold release layer is introduced as an intermediary between the molding compound and the conductive posts. This release layer prevents direct adhesion between the molding compound and conductive posts, eliminating the warpage caused by lamination while still providing protection to the conductive posts during the molding process.
2Quantity of substance
If high density packages with less than 300 μm bump pitch are used, then interconnect density is improved, but the chance for bump shorts increases
Solution Approach 1:
The mold release layer acts as a mediator that prevents direct contact between adjacent bumps during the molding process. By providing a non-adhesive interface, it maintains spacing between bumps and prevents shorts while allowing high-density interconnect configurations with pitches less than 300 μm.
Solution Approach 2:
A thin mold release layer is applied over the bumps before molding. This thin film provides physical separation and prevents bump-to-bump adhesion, enabling high-density packaging without increasing the risk of bump shorts.
Data Source
AI summary
A semiconductor device has a substrate. An electrical component is disposed over a first surface of the substrate. A solder paste is disposed over the first surface of the substrate. A conductive pillar is disposed on the solder paste. An encapsulant is deposited over the first surface of the substrate, the electrical component, and the conductive pillar. A solder bump is formed over the conductive pillar.