Dual-Sided Array Substrate Layout for Higher Pixel Resolution
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Solution Overview
Problem
Conventional IC designs using multiple types of transistors for pixel driving occupy a large area, reducing image resolution in display devices.
Innovation Solution
An array substrate structure with a first transistor on one surface of the substrate and a second transistor on the opposite surface, connected via a through via, utilizing different semiconductor materials for the transistors to reduce overall transistor area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple types of transistors are used for pixel driving, then the advantages of both polysilicon and metal oxide transistors are achieved, but the transistor area increases and image resolution decreases
Solution Approach 1:
The patent moves the second transistor from the front surface to the back surface of the substrate, utilizing the z-dimension (vertical space) to reduce the footprint on the display area. This spatial reconfiguration allows both transistor types to coexist without increasing the planar area occupied on the front surface, thereby maintaining high image resolution while achieving the performance benefits of multiple transistor types.
Solution Approach 2:
The second transistor is positioned underneath the first transistor structure by extending to the back surface of the substrate. This nested arrangement allows the transistors to share the same lateral footprint, with the second transistor effectively 'nested' within the vertical space occupied by the first transistor, minimizing the overall area consumption.
2Reliability
If multiple types of transistors are used for pixel driving, then the advantages of both polysilicon and metal oxide transistors are achieved, but the image resolution is reduced
Solution Approach 1:
By relocating the second transistor to the back surface of the substrate, the patent eliminates the need for increased lateral spacing that would compromise display resolution. The vertical stacking in the z-dimension allows high-resolution pixel arrangements to be maintained on the front surface while accommodating multiple transistor types in the depth direction.
Solution Approach 2:
The patent segments the transistor structures into distinct layers at different surfaces of the substrate. The first transistor resides on the front surface with its active channel region, while the second transistor is positioned on the back surface with its semiconductor layer extending through the substrate thickness, allowing both to function independently without interfering with each other's performance or the display quality.
Data Source
AI summary
An array substrate structure is provided, which includes a substrate with a first surface and a second surface opposite to the first surface. A first TFT is on the first surface of the substrate, and a second TFT is on the second surface of the substrate. A through via passes through the substrate, and the first TFT is electrically connected to the second TFT through the through via.