Dual-Sided Memory Bit Line Layout for Lower RC Loading
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Solution Overview
Problem
As semiconductor integrated circuits (ICs) become smaller and more complex, the resistance of conductive lines within these digital devices affects operating voltages and overall IC performance, leading to inefficiencies.
Innovation Solution
The configuration of bit lines on both the front-side and back-side of a substrate, with one set on a metal layer above the front-side and another on a metal layer below the back-side of the substrate, reduces resistance capacitance (RC) loading, thereby increasing speed and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If ICs become smaller and more complex, then integration density increases, but resistance of conductive lines increases affecting operating voltages and performance
Solution Approach 1:
The patent extends the conductive path from a single-sided planar layout to a three-dimensional structure by routing bit lines through both the front-side and back-side of the substrate. This dimensional transition allows the bit lines to achieve longer effective lengths and lower resistance without increasing the planar footprint, thereby maintaining operating voltage stability while preserving high integration density.
2Speed
If bit lines are configured on both front-side and back-side of substrate, then RC loading is reduced increasing speed, but device complexity increases
Solution Approach 1:
The bit line interconnect is segmented into multiple sections: a first bit line on the front-side metal layer, a second bit line on the back-side metal layer, and intermediate connections through the substrate. This segmentation allows each segment to be optimized independently, reducing overall RC loading and improving signal transmission speed while managing structural complexity through modular design.
Solution Approach 2:
The dual-sided bit line configuration embeds the back-side bit line structure within the overall interconnect architecture, where the front-side and back-side metal layers are interconnected through vias and substrate connections. This nested arrangement allows efficient use of three-dimensional space, reducing RC loading without proportionally increasing device complexity.
3Loss of energy
If bit lines are configured on both front-side and back-side of substrate, then power consumption is reduced, but manufacturing complexity increases
Solution Approach 1:
By transitioning to three-dimensional interconnect routing using both front-side and back-side metal layers, the patent reduces the total length of conductive paths required to span the same logical distance. This dimensional approach lowers resistive power losses (I²R heating) while the manufacturing complexity is managed through standard semiconductor fabrication techniques including dual-sided metallization and via formation.
Data Source
AI summary
A memory cell array includes a first bank of memory cells, a second bank of memory cells adjacent to the first bank of memory cells, a first set of bit lines and a second set of bit lines. The first set of bit lines extend in a first direction, is coupled to the first bank of memory cells, and is on at least a first metal layer above a front-side of a substrate. The second set of bit lines extend in the first direction, is coupled to the second bank of memory cells, and is on at least a second metal layer below a back-side of the substrate opposite from the front-side of the substrate.