Dual-Sided Capacitor Structure for High Capacitance and Rated Voltage
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Solution Overview
Problem
Existing capacitor structures in semiconductor packages face challenges in achieving high-rated voltage characteristics and increased capacitance, which are essential for high-performance and miniaturized electronic devices.
Innovation Solution
A capacitor structure design featuring a base substrate with through vias connecting symmetrical sub-capacitor structures on both surfaces, each comprising lower and upper electrodes with capacitor dielectric layers, and a mold layer to enhance electrical connectivity and symmetry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional single-sided capacitor structure is used, then the device complexity is low, but the capacitance and rated voltage characteristics are insufficient
Solution Approach 1:
The patent transitions from a conventional single-sided capacitor structure to a dual-sided three-dimensional structure by placing sub-capacitor structures on both the top and bottom surfaces of the base substrate, connected through through-vias. This dimensional change enables improved rated voltage characteristics and capacitance without proportionally increasing complexity
Solution Approach 2:
The capacitor structure is divided into multiple sub-capacitor structures (first and second sub-capacitor structures) with separate lower and upper electrodes, dielectric layers, and connection paths through through-vias. This segmentation allows each sub-structure to contribute independently to the overall capacitance and voltage handling capability
2Reliability
If the capacitor structure is miniaturized for high-performance electronic devices, then the device size is reduced, but achieving high capacitance and rated voltage characteristics becomes more difficult
Solution Approach 1:
By utilizing both top and bottom surfaces of the base substrate and extending through-vias vertically, the patent creates a three-dimensional capacitor configuration that increases effective capacitance volume without proportionally increasing the horizontal footprint, enabling miniaturization while maintaining high capacitance
Solution Approach 2:
The patent merges multiple functional elements (multiple sub-capacitor structures, through-vias, mold layers) into a compact integrated assembly where components are stacked and interconnected in three dimensions, achieving high capacitance in a reduced volume
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design improves rated voltage characteristics and increases capacitance by ensuring efficient electrical connections and symmetry between sub-capacitor structures, enhancing the performance of semiconductor packages.
Implementation Method 1
a first through via extending through the base substrate in a vertical direction perpendicular to the top surface of the base substrate and electrically connecting the first lower electrode to the second lower electrode
Implementation Method 2
a first sub-capacitor structure disposed on the bottom surface of the base substrate and including a first lower electrode electrically connected to a first end of the through via, a first upper electrode, and a first capacitor dielectric layer between the first lower electrode and the first upper electrode
Data Source
AI summary
A capacitor structure includes a base substrate, a through via extending in a vertical direction from a top surface of the base substrate to a bottom surface of the base substrate, a first sub-capacitor structure disposed on the bottom surface of the base substrate and including a first lower electrode electrically connected to a first end of the through via, a first upper electrode, and a first capacitor dielectric layer between the first lower electrode and the first upper electrode, and a second sub-capacitor structure disposed on the top surface of the base substrate and including a second lower electrode electrically connected to a second end, opposite to the first end, of the through via, a second upper electrode, and a second capacitor dielectric layer between the second lower electrode and the second upper electrode on the top surface of the base substrate.