Dual-Sided Chip Packaging Structure for High-Speed Interconnection
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Solution Overview
Problem
Current semiconductor packaging structures face challenges in achieving high-speed and small-volume interconnection between chips, limiting the integration level and electrical connection of both sides of the chip to an external circuit.
Innovation Solution
A packaging structure that includes a substrate, a device chip with both sides electrically connected to the substrate through a conductive pillar and redistribution structures, enabling electrical connection of both the front and back sides of the chip to the substrate and subsequently to an external circuit, along with conductive bumps and sealing layers for enhanced integration and protection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional chip manufacturing technologies are used for monolithic chip sizes, then manufacturing processes are simplified, but the ability to achieve large size integrated circuits with high-speed interconnection is limited
Solution Approach 1:
The chip is divided into two opposite sides (first side and second side), each capable of electrical connection to the substrate. The first side connects through bonding pads, while the second side connects through conductive bumps, enabling both sides to function independently for high-speed interconnection.
Solution Approach 2:
The patent utilizes the third dimension by forming conductive pillars that extend vertically from the substrate through the packaging structure, enabling electrical connection to the second side of the chip from the opposite direction, thus adding a vertical interconnection dimension.
2Adaptability or versatility
If Si bridge chips are embedded in the silicon substrate for heterogeneous chip packaging, then interconnection between chips is enabled, but the packaging structure becomes complex
Solution Approach 1:
The packaging structure is designed to universally accommodate both single-sided and dual-sided chip connections. The substrate and packaging layers can support either conventional single-sided bonding or the enhanced dual-sided configuration with conductive bumps, providing multi-functionality without requiring entirely different packaging solutions.
Solution Approach 2:
The conductive pillars and packaging layers serve as intermediaries that facilitate electrical connection between the substrate and the second side of the chip. These intermediary structures enable heterogeneous chip packaging without requiring direct embedding of Si bridge chips, thereby reducing structural complexity.
3Reliability
If only the front side of the chip is electrically connected to the substrate, then the packaging structure is simple, but the integration level and electrical connection of both sides of the chip is limited
Solution Approach 1:
Different regions of the chip are provided with different connection methods: the first side (front side) uses conventional bonding pads for electrical connection, while the second side (back side) uses conductive bumps. This local differentiation allows each side to be optimized for its specific function while achieving high integration.
Solution Approach 2:
The conductive bumps are formed on the second side of the chip in advance during chip fabrication, and the packaging structure is designed to accommodate these pre-formed bumps. This preliminary action enables dual-sided connection capability to be built into the chip itself, reducing the need for complex post-packaging modifications.
Data Source
AI summary
A packaging structure and a packaging method are provided. The packaging method includes: providing a carrier; forming a first redistribution structure on the carrier, the first redistribution structure including a first area and a second area; forming a conductive pillar on the first redistribution structure in the first area, the conductive pillar being electrically connected to the first redistribution structure; providing a device chip, including a first side and a second side opposite to the first side; bonding the second side of the device chip to the first redistribution structure in the second area, the device chip being electrically connected to the first redistribution structure; providing a substrate including a bonding surface; and bonding the first side of the device chip and the conductive pillar to the bonding surface, the device chip being electrically connected to the substrate, and the conductive pillar being electrically connected to the substrate.