Dual-Sided Chip on Film Package With Embedded Vias
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Chip on film (COF) semiconductor packages face inefficiencies in space utilization, as they typically mount chips on a single surface of a film substrate, limiting the effective use of available space and design flexibility.
Innovation Solution
The COF package design includes mounting chips on both surfaces of a flexible film with patterned circuit layers, connected via vias, and using solder resist layers to expose specific areas for chip mounting, allowing for improved space utilization and design flexibility by enabling dual-sided chip placement and electrical connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If chips are mounted on a single surface of the film substrate, then the manufacturing process is simple, but the space utilization efficiency is low
Solution Approach 1:
The patent transitions from single-sided chip mounting to dual-sided chip mounting by utilizing both surfaces of the flexible film substrate. This dimensional change allows chips to be mounted on the front surface and back surface simultaneously, effectively doubling the space utilization efficiency while maintaining manufacturing simplicity through standardized processes.
Solution Approach 2:
The patent employs a flexible film substrate that can be bent and folded, enabling dual-sided chip mounting. The flexibility of the thin film allows it to accommodate chips on both surfaces without compromising structural integrity, thereby improving space utilization while keeping the manufacturing process manageable.
2Area of stationary object
If chips are mounted on both surfaces of the flexible film, then the space utilization efficiency is improved, but the electrical connectivity complexity increases
Solution Approach 1:
The patent implements a nested structure where conductive vias are embedded within the flexible film substrate to electrically connect chips mounted on opposite surfaces. The vias are nested inside the film thickness, creating internal electrical pathways that simplify the overall connectivity architecture despite dual-sided mounting.
Solution Approach 2:
The flexible film substrate acts as an intermediary element that provides both mechanical support and electrical connectivity between chips on opposite surfaces. The conductive vias within the substrate serve as mediators, transferring electrical signals between front and back surface chips without requiring external wiring.
3Adaptability or versatility
If the flexible film is made thinner to improve flexibility, then the design flexibility is improved, but the structural strength decreases
Solution Approach 1:
The patent uses composite material structures for the flexible film substrate, combining multiple layers with different properties. This includes flexible polymer layers for bendability and reinforcing layers for structural strength, allowing the substrate to be thin yet sufficiently strong to support dual-sided chip mounting.
Solution Approach 2:
The patent applies local quality enhancement by adding reinforcement elements specifically at high-stress areas such as chip mounting regions and via locations. The flexible film maintains thinness in non-critical areas while having localized strength enhancements where needed, optimizing both flexibility and structural integrity.
Data Source
AI summary
A chip on film package including a flexible film, a first patterned circuit layer, one or more first chips, a second patterned circuit layer, and one or more second chips. The flexible film includes a first surface and a second surface opposite to the first surface. The first patterned circuit layer is disposed on the first surface. The one or more first chips are mounted on the first surface and electrically connected to the first patterned circuit layer. The second patterned circuit layer is disposed on the second surface. The one or more second chips are mounted on the second surface and electrically connected to the second patterned circuit layer.