Semiconductor Package Assembly Using Dual-Sided Core Substrates
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Solution Overview
Problem
The semiconductor industry faces challenges in integrating a high number of components within a compact device package while maintaining power and signal integrity, particularly in applications requiring high-speed data processing and complex calculations, due to limitations in existing packaging technologies.
Innovation Solution
The method involves forming a device package by bonding component devices on opposite sides of a core substrate with pre-soldered controlled collapse chip connection (C4) bumps, using a redistribution structure and interconnect structure with conductive connectors to achieve better integration and reduced transmission losses, allowing for higher component density and improved computing performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If component devices are integrated at high density within a compact package, then integration density and computing performance are improved, but power and signal integrity deteriorate due to closer spacing and transmission losses
Solution Approach 1:
An organic core substrate is introduced as an intermediary platform to bond component devices on both its first and second major surfaces. This core substrate acts as a mediator that enables high-density integration while maintaining power and signal integrity through its pre-soldered C4 bumps and redistribution structure, resolving the contradiction between integration density and reliability.
2Quantity of substance
If contact pads are arranged at small pitch to increase I/O functionality, then integration density is improved, but manufacturing complexity and difficulty increase
Solution Approach 1:
The patent transitions from planar contact pad arrangements to a three-dimensional configuration by bonding component devices on both the first and second major surfaces of the core substrate. This vertical stacking approach increases I/O functionality without requiring smaller pitch on individual surfaces, thereby reducing manufacturing complexity while improving integration density.
3Area of stationary object
If component devices are placed closer together to reduce package size, then miniaturization is achieved, but transmission losses and signal integrity worsen
Solution Approach 1:
The package is segmented into multiple functional layers: the core substrate with its redistribution structure, component devices on the first major surface, and additional component devices on the second major surface. This segmentation allows compact packaging while maintaining signal integrity through the organized interconnect structure and pre-soldered C4 bumps that minimize transmission paths.
4Ease of manufacture
If redistribution structure is used to fan-out wiring for larger pitch contacts, then manufacturing ease and cost are improved, but device complexity increases
Solution Approach 1:
The core substrate is prepared in advance with pre-soldered C4 bumps and a redistribution structure that includes multiple conductive layers and vias. This preliminary preparation simplifies the subsequent bonding process and assembly steps, making manufacturing easier while the structured redistribution pattern manages the complexity of signal routing between different pitch requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the integration of more component devices closer together, enhancing power and signal integrity, which leads to improved computing performance and faster data processing in high-performance computing applications.
Implementation Method 1
pre-soldered controlled collapse chip connection (C4) bumps
Implementation Method 2
interconnect structure with conductive connectors to achieve better integration
Data Source
AI summary
A method includes forming a redistribution structure on a carrier substrate, coupling a first side of a first interconnect structure to a first side of the redistribution structure using first conductive connectors, where the first interconnect structure includes a core substrate, where the first interconnect structure includes second conductive connectors on a second side of the first interconnect structure opposite the first side of the first interconnect structure, coupling a first semiconductor device to the second side of the first interconnect structure using the second conductive connectors, removing the carrier substrate, and coupling a second semiconductor device to a second side of the redistribution structure using third conductive connectors, where the second side of the redistribution structure is opposite the first side of the redistribution structure.