Through-Die Via Inductance Reduction in Dual-Sided Die Stacks
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Solution Overview
Problem
Conventional electronic assemblies with all memory dies stacked on one side of a processor die experience increased inductance in through-silicon vias (TSVs), which limits performance and operating frequency.
Innovation Solution
Distributing memory dies on both sides of the processor die, with through-die vias connecting them, reduces the length and inductance of electrical connections, allowing for higher operating frequencies and lower power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If all memory dies are stacked on one side of a processor die, then the structure is simpler and easier to manufacture, but the inductance in through-silicon vias increases, limiting performance and operating frequency
Solution Approach 1:
The patent divides the memory die stack into two separate groups: one group stacked on the first side of the processor die, and another group stacked on the second side. This segmentation reduces the number of through-silicon vias required and decreases the total inductance of the electrical connections, thereby enabling higher operating frequencies while maintaining manufacturing simplicity
Solution Approach 2:
The patent utilizes the third dimension (vertical stacking) on both sides of the processor die to distribute memory dies. By transitioning from a single-sided vertical stack to a dual-sided vertical stack configuration, the patent reduces the length and inductance of through-silicon vias while maintaining high component density, thus resolving the contradiction between structural simplicity and operating speed
2Ease of manufacture
If all memory dies are stacked on one side of a processor die, then alignment and bonding are simpler, but inductance increases causing higher power consumption
Solution Approach 1:
The patent segments the memory die configuration into two independent stacks on opposite sides of the processor die. This segmentation reduces the total length of through-silicon vias and their associated inductance, which directly reduces power consumption during data transmission while keeping the alignment and bonding processes relatively simple through symmetric placement
3Ease of operation
If through-silicon vias are used to connect stacked memory dies, then vertical connections are achieved, but inductance increases limiting performance
Solution Approach 1:
The patent divides the memory die stack into two separate stacks positioned on opposite sides of the processor die. This segmentation reduces the total number and length of through-silicon vias required, thereby decreasing overall inductance and enabling faster data transmission speeds while preserving the vertical connection architecture
Solution Approach 2:
Instead of stacking all memory dies on one side (conventional approach), the patent inverts the configuration by distributing stacks to both sides of the processor die. This inversion reduces the path length and inductance of through-silicon vias, improving data transmission speed while maintaining vertical connection capabilities
Data Source
AI summary
An electronic assembly includes a processor die assembly, a first die assembly, and a second die assembly. The first die assembly is positioned on a first side of the processor die assembly. The second die assembly is positioned on a second side of the processor die assembly opposite the first side of the processor die assembly. Through-die vias couple the first and second die assemblies to the processor die assembly.