Dual-Sided HBM Die Stacking to Reduce Warpage and Signal Delay
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Solution Overview
Problem
High-bandwidth memory (HBM) semiconductor packages face challenges with signal delay and manufacturing defects due to the increased risk of warpage when multiple core dies are stacked, limiting the number of dies that can be stacked for high processing speed and bandwidth.
Innovation Solution
A semiconductor package design where core dies are stacked on both surfaces of a base die, with a redistribution layer, physical layer interface, and direct access interface, using copper pillars or wires for electrical connections, to enhance structural stability and reduce signal delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If more core dies are stacked to increase bandwidth, then the bandwidth increases, but the risk of signal delay and manufacturing defects increases
Solution Approach 1:
The patent transitions from stacking dies in a single vertical direction to stacking dies in multiple directions (both surfaces of the base die). This dimensional change allows increasing the number of stacked dies without proportionally increasing the vertical distance, thereby maintaining signal integrity while achieving higher bandwidth through parallel stacking paths.
Solution Approach 2:
The patent divides the stacking configuration into two separate groups: a first group of core dies stacked on the first surface and a second group of core dies stacked on the second surface. This segmentation distributes the thermal and mechanical loads across different regions, reducing warpage risk and signal delay while collectively increasing the total number of stacked dies for higher bandwidth.
2Productivity
If more core dies are stacked, then the bandwidth increases, but the distance between the uppermost core die and the base die increases causing latency
Solution Approach 1:
By utilizing both surfaces of the base die for stacking, the patent creates parallel signal paths that distribute data transmission loads. This reduces the effective communication distance for individual signal paths while maintaining high overall bandwidth, thereby reducing latency without sacrificing productivity.
3Productivity
If more core dies are stacked, then the bandwidth increases, but the risk of warpage due to repeated heating increases
Solution Approach 1:
The patent segments the stacked dies into two groups located on opposite surfaces of the base die. This spatial segmentation distributes the thermal load from repeated heating processes across different regions, preventing concentrated thermal stress that causes warpage. The base die acts as a thermal buffer, maintaining structural stability while enabling higher bandwidth through increased die stacking.
4Device complexity
If core dies are stacked on one surface, then the structure is simple, but the structural stability is reduced and warpage occurs
Solution Approach 1:
The patent employs an asymmetric stacking configuration where core dies are distributed on both surfaces of the base die rather than concentrated on one surface. This asymmetric distribution creates a more balanced structural centroid, improving overall structural stability and reducing warpage susceptibility while maintaining manageable device complexity through standardized stacking processes.
Data Source
AI summary
A semiconductor package according to an example includes a base die having a first surface and a second surface opposite each other; a first group of core dies stacked on the first surface of the base die and electrically connected to the base die; a mount member facing the second surface of the base die; a second group of core dies between the base die and the mount member, the second group of core dies being stacked on the second surface of the base die and electrically connected to the base die; and an interface for an electrical connection between the base die and the mount member.