Dual-Sided IC Carrier Structure for Backside Power and Heat Dissipation
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Solution Overview
Problem
The scaling of multi-gate and nanowire transistors in integrated circuits faces challenges such as constraints on lithographic processes, trade-offs between feature dimension and spacing, and heat dissipation issues, particularly due to in-plane distortions and thermal resistance in conventional carrier wafer bonding processes.
Innovation Solution
The use of alternative carriers like amorphous silicon or crystalline silicon with compliant bonding layers to reduce non-linear strain and improve heat dissipation, allowing for more efficient power delivery and interconnect pitch, and enabling backside power delivery to reduce power network resistance and enhance performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional carrier wafer bonding processes are used, then device fabrication can proceed, but in-plane distortions and thermal resistance increase, degrading manufacturing precision and heat dissipation
Solution Approach 1:
The patent introduces an intermediate carrier wafer layer between the device wafer and the final substrate. This carrier wafer acts as a mediator that provides a flat, stable bonding surface while allowing the device wafer to be processed separately. The carrier wafer reduces in-plane distortions during bonding and improves backside edge placement error by providing a rigid support structure that maintains dimensional stability during subsequent processing steps.
Solution Approach 2:
The patent segments the wafer structure into multiple independent components: the device wafer containing the actual devices, the carrier wafer providing mechanical support and flatness, and the final substrate. This segmentation allows each component to be optimized independently - the device wafer for device performance, the carrier wafer for dimensional stability and flatness, and the substrate for final integration. The carrier wafer can be removed after bonding if needed, providing flexibility in the final structure.
2Power
If conventional carrier wafer bonding processes are used, then power delivery can be established, but power network resistance increases and heat dissipation becomes inefficient
Solution Approach 1:
The patent transitions from planar power delivery to three-dimensional power delivery by utilizing the vertical dimension through backside power delivery. Power and ground connections are established through the substrate and carrier wafer from the backside of the device wafer, creating vertical current paths that are perpendicular to the device plane. This dimensional change reduces the horizontal current path length and associated resistance, improving power delivery efficiency and heat dissipation.
3Productivity
If feature dimensions are scaled down to increase device density, then capacity increases, but lithographic process constraints and spacing requirements worsen
Solution Approach 1:
The patent segments the fabrication process into front-side device processing and backside interconnect processing. The front side focuses on forming high-density device structures using advanced lithography, while the back side handles interconnect formation and power delivery. This segmentation allows the front-side lithography to be optimized for maximum device density without being constrained by interconnect spacing requirements, as those are handled separately on the backside through different process steps that can use less stringent lithographic constraints.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves backside edge placement error, reduces power network resistance, and enhances performance by allowing for tighter pitch interconnects and more efficient heat removal, addressing the limitations of conventional carrier wafer bonding in high-bandwidth computing applications.
Implementation Method 1
compliant bonding layers to reduce non-linear strain
Implementation Method 2
improve heat dissipation
Data Source
AI summary
Structures having alternative carriers for dual-sided devices are described. In an example, an integrated circuit structure includes a front side structure including a device layer, and a plurality of metallization layers above the device layer. A backside structure is below the device layer. A carrier wafer or substrate is bonded directly to and is in contact with the front side structure, or is bonded to the front side structure by a compliant bonding layer.