Dual-Sided IC Registration Marks for Backside Power Alignment
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Solution Overview
Problem
The challenge of maintaining mobility improvement and short channel control in microelectronic devices as device dimensions scale below the 10 nanometer node, along with the trade-off between critical dimension and spacing in lithographic processes, is exacerbated by the need for high bandwidth computing and conventional power delivery methods that impact signal routing and performance.
Innovation Solution
Implementing backside power delivery and registration marks for dual-sided devices using metal gate cuts and fin trench isolation patterns, allowing for alignment in both X and Y directions without additional processing steps, and enabling efficient integration of nanowire-based and fin-based transistors with reduced power network resistance and increased layout flexibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional front-side power delivery is used, then power delivery is achieved, but signal routing flexibility is reduced and power network resistance increases
Solution Approach 1:
The patent inverts the conventional power delivery approach by delivering power from the backside of the substrate rather than the front side. This allows power networks to be routed independently from signal routes on the front side, reducing interference and improving routing flexibility while lowering power network resistance through optimized current paths.
Solution Approach 2:
The patent utilizes the vertical dimension by implementing backside power delivery, effectively adding a third dimension to the power distribution architecture. This separates power routing from signal routing in the vertical axis, allowing both to be optimized independently without compromising either function.
2Productivity
If device dimensions are scaled down below 10 nanometer node, then device density is increased, but maintaining mobility improvement and short channel control becomes challenging
Solution Approach 1:
The patent segments the transistor structure into multiple gates surrounding the channel (multi-gate transistors), providing enhanced control over the channel region. This segmentation allows for improved short channel control at scaled dimensions by distributing the control function across multiple gate structures that can independently manage different aspects of channel behavior.
Solution Approach 2:
The patent implements different material compositions and structural characteristics in different regions of the transistor to optimize local properties. For example, using high-k dielectric materials in specific gate regions or varying channel materials to maintain mobility improvement while achieving the necessary short channel control at sub-10nm nodes.
3Manufacturing precision
If lithographic processes are used to pattern smaller features, then critical dimension is reduced, but spacing between features must be increased
Solution Approach 1:
The patent employs self-aligned patterning processes where features are created in periodic sequences with each processing step automatically aligning to previous features. This periodic fabrication approach allows for reduced critical dimensions while maintaining appropriate spacing through cumulative self-alignment rather than relying solely on single-step lithographic resolution.
4Adaptability or versatility
If dual-sided devices are implemented, then layout flexibility is increased, but alignment precision between sides must be maintained
Solution Approach 1:
The patent incorporates registration marks and alignment features during the initial fabrication stages that persist through subsequent processing. These preliminary alignment structures enable precise registration between front-side and back-side features without requiring additional alignment steps, thus maintaining manufacturing precision while enabling dual-sided device flexibility.
Data Source
AI summary
Structures having registration marks for dual-sided devices are described. In an example, an integrated circuit structure includes a front side structure. The front side structure includes a device layer comprising a plurality of nanowire-based or fin-based transistors and a pad laterally adjacent to the plurality of nanowire-based or fin-based transistors, the pad having first grating structures aligned along an X-direction and second grating structures aligned along a Y-direction therein, the first and second grating structures exposed at a backside surface of the front side structure. The front-side also includes a plurality of metallization layers above the plurality of nanowire-based or fin-based transistors. The integrated circuit structure also includes a backside structure below the plurality of nanowire-based or fin-based transistors of the device layer of the front side structure, the backside structure comprising backside metal layers and vias.