Dual-Sided High-Density Interconnect Substrate for Compact Packaging
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Solution Overview
Problem
There is a need for packages with substrates that provide better performance and reduced size while enabling high-density and high-speed communication between integrated devices.
Innovation Solution
The package includes a substrate with at least one dielectric layer, featuring high-density interconnects on both surfaces, allowing for dense electrical routing and reduced package size, fabricated using a method that involves forming seed layers, interconnects, and dielectric layers, and coupling carriers to achieve high-density interconnects on both sides of the substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If high-density interconnects are implemented on both surfaces of the substrate, then communication speed and density between integrated devices are improved, but manufacturing complexity increases
Solution Approach 1:
The substrate is divided into two separate surfaces, each with its own set of high-density interconnects. The first surface contains a first plurality of high-density interconnects, while the second surface contains a second plurality of high-density interconnects. This segmentation allows independent optimization and manufacturing of each surface's interconnect structure, reducing overall manufacturing complexity while maintaining high communication speed capability.
Solution Approach 2:
The patent transitions from single-sided interconnection to dual-sided interconnection by utilizing the third dimension (the other surface of the substrate). This dimensional change enables high-density interconnects to be formed on both surfaces, effectively doubling the communication capacity without increasing the footprint area, thus improving communication speed while managing manufacturing complexity through systematic process design.
2Volume of moving object
If high-density interconnects are implemented on both surfaces of the substrate, then package size is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The manufacturing process is segmented into separate stages for each surface. Seed layers are formed independently on the first and second surfaces, followed by separate electroplating processes to form interconnects on each surface. This segmentation allows standard precision manufacturing processes to be applied to each surface individually, avoiding the need for excessively tight tolerances that would be required if both surfaces were processed simultaneously as a single complex structure.
Solution Approach 2:
Seed layers are formed preliminarily on both surfaces before the actual interconnect formation. These seed layers serve as templates that guide subsequent electroplating processes, ensuring precise interconnect formation without requiring complex real-time control during the plating process itself. This preliminary action simplifies the precision requirements by establishing a controlled foundation before the main interconnect formation occurs.
3Speed
If multiple types of interconnects with different dimensions are used, then communication performance is optimized, but device complexity increases
Solution Approach 1:
Different regions of the substrate are assigned different interconnect characteristics based on local communication requirements. The first surface may have interconnects optimized for certain signal types or density requirements, while the second surface has interconnects optimized for different requirements. This local quality approach allows performance optimization in specific areas without requiring all interconnects throughout the device to be complex, thereby managing overall device complexity while maintaining high communication performance where needed.
Data Source
AI summary
A package that includes a substrate, a first integrated device coupled to a first surface of the substrate, and a second integrated device coupled to a second surface of the substrate. The substrate includes at least one dielectric layer, a first plurality of high-density interconnects located in the at least one dielectric layer and through a first surface of the at least one dielectric layer; a second plurality of high-density interconnects located in the at least one dielectric.