Dual-Sided Memory Data Lines Reduce RC Latency
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Solution Overview
Problem
Existing memory devices face challenges in optimizing metal track arrangement to reduce latency in signal transmission and save area, particularly as the number of memory cells increases, leading to high resistance and capacitance issues in data lines.
Innovation Solution
The use of back side conductive metal lines with larger widths to reduce resistance and capacitance in data lines, coupled with dual-sided data lines for each memory bank, which optimizes operational speed and reduces area requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If conventional metal track arrangement is used, then manufacturing is simpler, but resistance and capacitance in data lines increase leading to higher latency
Solution Approach 1:
The patent utilizes both front-side and back-side metal layers to route data lines, transitioning from a planar single-sided layout to a three-dimensional dual-sided architecture. This allows data lines to be routed on the back side of the substrate, reducing the number of vias and interconnections required on the front side, thereby reducing RC latency while distributing the complexity across multiple dimensions.
Solution Approach 2:
The memory device is divided into multiple memory segments with dedicated data lines for each segment. The back-side metal layers are segmented to provide separate data line paths for different memory segments, allowing independent optimization of each segment's data line routing to minimize resistance and capacitance specific to each segment's location and size.
2Speed
If larger width metal lines are used, then resistance and capacitance decrease improving speed, but area occupied by metal tracks increases
Solution Approach 1:
By routing data lines on the back side of the substrate using additional metal layers, the patent effectively adds a vertical dimension to the metal track arrangement. This allows for larger width metal lines to be implemented without proportionally increasing the planar footprint, as the back-side routing shares the substrate area with the front-side circuitry through vertical stacking rather than lateral expansion.
3Area of stationary object
If dual-sided data lines are implemented, then transition area and macro area are reduced, but manufacturing process complexity increases
Solution Approach 1:
The patent implements dual-sided data lines by utilizing back-side metal layers that are formed through standard semiconductor manufacturing processes extended to multiple layers. The transition area is reduced by routing data lines vertically through vias from the front side to the back side, where they continue their path without requiring large transition regions. The manufacturing complexity is managed by using established multi-layer metal formation techniques.
4Quantity of substance
If more memory cells are integrated, then device functionality increases, but resistance and capacitance in data lines increase causing performance degradation
Solution Approach 1:
The memory device is segmented into multiple independent memory segments, each with its own dedicated data lines routed through the back-side metal layers. This segmentation allows each segment to have optimized, shorter data line paths with lower resistance and capacitance, preventing the cumulative RC effects that would occur in a monolithic design. Each segment can be independently optimized for its specific size and location.
Solution Approach 2:
By routing data lines on the back side of the substrate, the patent creates shorter and more direct signal paths that reduce the number of vias and interconnections required. This three-dimensional routing approach reduces the total length and complexity of data lines serving multiple memory cells, thereby reducing cumulative resistance and capacitance even as the number of memory cells increases.
Data Source
AI summary
A memory device in an integrated circuit is provided, including an input/output (I/O) circuit, a first memory segment and a second memory segment that separated from the first memory segment in a first direction, a first pair of data lines on a first side of the integrated circuit, extending in the first direction and configured to couple the first memory segment to the I/O circuit, and a second pair of data lines separated from the first pair of data lines in a second direction, different from the first direction, on a second side, opposite to the first side, of the integrated circuit, and configured to couple the second memory segment to the I/O circuit. A first width of the first pair of data lines is different from a second width of the second pair of data lines.