Symmetric Dual-Sided MOS IC Layout for Low-Harmonic RF Switching
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Solution Overview
Problem
Existing dual-sided MOS IC RF switches suffer from asymmetry in parasitic capacitances, leading to higher harmonic distortion and imbalance, particularly second-order harmonics, which affect RF switch performance.
Innovation Solution
A dual-sided MOS IC layout is designed with symmetric source and drain connections and front-to-backside connections, balancing parasitic capacitances through rotational and reflectional symmetries to reduce second-order harmonics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If asymmetric source and drain connections are used in dual-sided MOS IC, then device complexity is reduced, but parasitic capacitance imbalance increases leading to higher harmonic distortion
Solution Approach 1:
The patent applies asymmetry in reverse - it deliberately introduces symmetry where traditionally asymmetry would be used. The source and drain connections are configured with symmetric parasitic capacitances (Cs1=Cs2 and Cd1=Cd2) through symmetric layout design, which eliminates the harmful second-order harmonics while maintaining manageable device complexity through systematic design rules
2Object-generated harmful factors
If symmetric source and drain connections are implemented, then parasitic capacitance balance is improved reducing second-order harmonics, but layout complexity increases
Solution Approach 1:
The layout is segmented into symmetric units where each source and drain connection has matching parasitic capacitance values. The transistor array is divided into pairs with symmetric source connections (Cs1=Cs2) and drain connections (Cd1=Cd2), making the symmetry manageable through modular design rather than overwhelming complexity
Solution Approach 2:
The patent changes the design parameters by equating parasitic capacitance values (Cs1=Cs2 and Cd1=Cd2) through controlled layout geometry. By adjusting connection lengths, widths, and positions to achieve equal capacitance values, the design transforms the complexity from arbitrary to systematic and calculable
3Reliability
If front-to-backside connections are added for symmetric layout, then RF switch isolation is improved, but manufacturing complexity increases
Solution Approach 1:
The patent utilizes the third dimension (vertical stacking) by connecting source and drain between front and back sides of the substrate. This vertical interconnection approach achieves symmetric parasitic capacitance balancing without requiring complex lateral routing, improving RF isolation while keeping manufacturing feasible through standard through-substrate via techniques
Data Source
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AI summary
A dual-sided MOS IC includes an isolation layer and a MOS transistor. The isolation layer separates the MOS IC into a MOS IC frontside and a MOS IC backside. The MOS transistor is on both the MOS IC frontside and the MOS IC backside. The MOS transistor includes MOS gates, a first source connection in a first subsection of the MOS IC frontside, and a second source connection in a second subsection of the MOS IC backside. The first and second source connections are electrically coupled together through a first front-to-backside connection extending through the isolation layer. The MOS transistor further includes a first drain connection in the first subsection of the MOS IC backside, and a second drain connection in the second subsection of the MOS IC frontside. The first and second drain connections are electrically coupled together through a second front-to-backside connection extending through the isolation layer.