Dual-Sided Electro-Optical Assembly for Shorter SerDes Signal Paths
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Solution Overview
Problem
Existing co-packaged optics (CPO) and near-packaged optics (NPO) assemblies face challenges with high-speed connections between optical engines (OEs) and switch application-specific integrated circuits (ASICs) due to long electrical paths and significant bandwidth and power consumption, as well as stress and warpage issues that limit substrate size and design flexibility.
Innovation Solution
A dual-sided electro-optical assembly design where optical engines (OEs) are arranged on one side of the substrate opposite the integrated circuit (IC) and serializer/deserializer (SerDes), with high-speed signal channels traversing through the substrate to minimize path lengths and separate power channels, allowing for compact packaging and reduced stress.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If optical engines are arranged coplanarly surrounding the ASIC on the same substrate, then integration is achieved, but high-speed connection path lengths become several tens of millimeters long causing significant bandwidth loss and power consumption
Solution Approach 1:
The patent transitions from a coplanar two-dimensional arrangement where all components reside on the same side of the substrate to a three-dimensional dual-sided configuration. Optical engines are positioned on one side of the substrate while the ASIC is positioned on the opposite side, with high-speed electrical connections traversing through the substrate thickness. This dimensional change dramatically shortens the connection path lengths from tens of millimeters to sub-millimeter scales, reducing bandwidth loss and power consumption while maintaining integration.
2Adaptability or versatility
If the substrate size is increased to accommodate more components, then component placement flexibility improves, but stress and warpage issues arise that limit further scaling
Solution Approach 1:
By utilizing the third dimension (substrate thickness) to separate optical engines and ASIC onto opposite sides, the patent enables compact packaging that reduces the overall substrate footprint. This vertical stacking approach maintains component placement flexibility while avoiding the stress and warpage problems associated with large-area coplanar substrates.
3Ease of manufacture
If electrical connection paths are lengthened to accommodate routing challenges, then manufacturing ease improves, but signal integrity deteriorates due to transmission loss
Solution Approach 1:
The patent routes high-speed electrical signals through the substrate thickness dimension rather than along the surface plane. This vertical routing approach through vias and through-silicon connections dramatically shortens the electrical path lengths compared to coplanar routing, thereby maintaining signal integrity and reducing transmission loss while remaining manufacturable using standard through-silicon via and flip-chip techniques.
Data Source
AI summary
Electro-optical assemblies are disclosed. In one aspect, an electro-optical assembly includes a substrate having a first side and a second side opposing the first side. The electro-optical assembly also includes an optical engine (OE) coupled with the first side of the substrate. The electro-optical assembly further includes a serializer/deserializer (SerDes) coupled with the second side of the substrate, as well as an integrated circuit (IC) coupled with the second side of the substrate. The IC is electrically coupled with the SerDes. The OE is electrically coupled with the SerDes by way of a signal channel that traverses through the substrate between the first side and the second side.