Semiconductor Package Stacking With Dual-Sided Die Mounting
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Solution Overview
Problem
Semiconductor devices occupy significant PCB area due to long lead lengths between first and second semiconductor dies, leading to propagation delays and reduced operating efficiency.
Innovation Solution
The semiconductor device is designed with electrical components disposed above and below a substrate, utilizing a leadframe with exposed leads to minimize lead length and enhance electrical connections, allowing for efficient package stacking and reduced propagation delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a first semiconductor die within a first package is mounted to the PCB with long lead length to a second semiconductor die in a second package, then the semiconductor die can be mounted to the PCB with exposed leads making electrical connection, but the long lead length results in propagation delays and lower operating efficiency
Solution Approach 1:
The patent transitions from a planar two-dimensional PCB mounting arrangement to a three-dimensional stacked configuration. Multiple semiconductor packages are vertically stacked with electrical components disposed above and below a substrate, converting horizontal lead routing into vertical interconnections. This dimensional change dramatically reduces lead length between semiconductor dies while maintaining electrical connectivity, thereby reducing propagation delay and improving operating efficiency.
2Reliability
If a semiconductor die is mounted to a leadframe and encapsulated in a semiconductor package with exposed leads, then the semiconductor die is protected with structural support, but the package occupies significant area of the PCB
Solution Approach 1:
The patent employs vertical stacking of multiple semiconductor packages in the third dimension, allowing multiple devices to occupy a reduced PCB footprint. By disposing electrical components above and below the substrate and using vertical interconnects, the design achieves high component density while maintaining the protective encapsulation and structural support of traditional packages.
Solution Approach 2:
The patent implements nested packaging where multiple semiconductor packages are stacked vertically, with each package containing encapsulated semiconductor dies. The packages are arranged in a nested configuration where outer packages provide structural support and protection to inner packages, maximizing space utilization and reducing overall PCB area occupation while maintaining individual package integrity and environmental protection.
Data Source
AI summary
A semiconductor device has a substrate with a die mounting site and a plurality of leads. A first electrical component is disposed over a first surface of the die mounting site. A second electrical component is disposed over a second surface of the die mounting site opposite the first surface of the die mounting site. A first bond wire is coupled between the first electrical component and a first lead, and a second bond wire is coupled between the second electrical component and a second lead. A first encapsulant is deposited over the first electrical component, and a second encapsulant is deposited over the second electrical component with the leads exposed between the first encapsulant and second encapsulant. The leads are exposed from the first encapsulant and second encapsulant on a side of the semiconductor device.