Dual-Sided Semiconductor Package Wiring for Signal and Power Congestion
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Solution Overview
Problem
The increasing demand for miniaturization and high-capacity semiconductor devices leads to congestion in power and signal transmission on the front side of semiconductor substrates, hindering efficient operation.
Innovation Solution
A semiconductor package design that utilizes both sides of the semiconductor chip for signal and power transmission, with separate wiring layers on opposite surfaces, and incorporates a package substrate with cavities to accommodate multiple chips, reducing bonding wire length and congestion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If power wiring and signal wiring are connected to the front side of the semiconductor substrate, then the active region can receive power and signals, but congestion occurs in supplying power and transmitting signals due to ultra-high integration
Solution Approach 1:
The patent applies dimensionality change by moving power wiring connections from the front side (2D plane) to the back side of the semiconductor substrate. This utilizes the third dimension (depth/thickness) of the substrate to resolve wiring congestion, allowing power and signal layers to be separated in the vertical dimension while maintaining high integration density on the front side.
2Productivity
If wiring space is increased on the front side to accommodate more power and signal connections, then more active regions can be supported, but the chip size increases
Solution Approach 1:
The invention resolves the area-productivity contradiction by utilizing the back side of the substrate as an additional dimension for wiring connections. This allows the front side area to be fully utilized for active regions while the back side provides dedicated power and signal routing space, effectively doubling the available wiring real estate without increasing chip footprint.
3Productivity
If multiple chips are stacked to increase capacity, then high-capacity packages are achieved, but bonding wire length increases causing electrical performance degradation
Solution Approach 1:
The patent extracts the power wiring function from the traditional bonding wire path and creates dedicated power transmission patterns on the package substrate that connect directly to the back side of chips. This separation of power and signal paths reduces bonding wire length and eliminates the harmful inductance and resistance associated with long bonding wires, thereby improving electrical performance while maintaining high package capacity.
Solution Approach 2:
The package substrate acts as an intermediary that provides direct electrical connections to the back side of stacked chips through through-vias and power transmission patterns. This intermediary structure eliminates the need for long bonding wires to traverse multiple chip layers, reducing electrical parasitics and improving signal integrity in high-capacity stacked packages.
Data Source
AI summary
According to the present invention, a semiconductor package is provided. A semiconductor package may include a package substrate, and a first semiconductor chip disposed on the package substrate, wherein the first semiconductor chip may include a semiconductor substrate including a first surface and a second surface opposite to the first surface, a circuit pattern region disposed on the first surface of the semiconductor substrate and including a plurality of circuit patterns, a signal wiring layer disposed on the circuit pattern region and electrically connected to the plurality of circuit patterns, and a power wiring layer disposed on the second surface of the semiconductor substrate and electrically connected to the plurality of circuit patterns through a plurality of through vias extending through the semiconductor substrate, and the package substrate may include a signal transmission pattern electrically connected to the signal wiring layer of the first semiconductor chip, and a power transmission pattern electrically connected to the power wiring layer of the first semiconductor chip.