Dual-Sided Pixel Isolation Structure for Low-Dark-Current Image Sensors
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Solution Overview
Problem
Existing image sensors face challenges in achieving improved electrical and optical characteristics, which are crucial for high-performance applications in various fields.
Innovation Solution
The image sensor design incorporates a semiconductor substrate with first and second pixel isolation structures that extend vertically from opposite surfaces, featuring a liner semiconductor pattern, a liner insulating pattern, and a capping insulating pattern to enhance pixel isolation and reduce dark current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If pixel isolation structures are formed to improve electrical isolation between pixels, then dark current is reduced, but manufacturing complexity increases due to multiple trench structures and material layers
Solution Approach 1:
The pixel isolation structure is divided into multiple segments: a first pixel isolation structure extending from the first surface and a second pixel isolation structure extending from the second surface. These segmented structures work together to provide complete electrical isolation while allowing simpler formation processes for each individual structure.
Solution Approach 2:
The isolation approach transitions from single-surface processing to dual-surface processing by forming the second pixel isolation structure from the second surface. This dimensional change allows the structures to meet within the substrate, providing effective isolation while simplifying the overall manufacturing approach.
2Object-affected harmful factors
If pixel isolation structures extend deeply into the substrate to improve optical isolation, then light absorption in non-pixel regions is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The deep isolation requirement is segmented into two shallower structures formed from opposite surfaces. The first pixel isolation structure extends from the first surface and the second pixel isolation structure extends from the second surface, meeting within the substrate. This segmentation reduces the depth control precision requirement for each individual structure while achieving the same total isolation depth.
Solution Approach 2:
Each pixel isolation structure extends partially through the substrate thickness rather than requiring one structure to extend fully. The first structure extends from the first surface to a first depth, and the second structure extends from the second surface to a second depth, with the sum of depths exceeding the substrate thickness to ensure complete isolation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design improves the electrical and optical characteristics of the image sensor by reducing dark current and enhancing light absorption, leading to better performance in applications such as digital cameras and medical micro cameras.
Implementation Method 1
a photoelectric conversion region disposed in the semiconductor substrate of each of the pixel regions
Data Source
AI summary
An image sensor includes a semiconductor substrate having a first surface and a second surface opposite to the first surface, a first pixel isolation structure disposed in a first trench which vertically extends from the first surface of the semiconductor substrate and defines a plurality of pixel regions, and a second pixel isolation structure disposed in a second trench vertically extending from the second surface of the semiconductor substrate. The second pixel isolation structure overlaps the first pixel isolation structure. The first pixel isolation structure includes a liner semiconductor pattern defining a gap region in the first trench, the liner semiconductor pattern including sidewall portions and a bottom portion connecting the sidewall portions, a liner insulating pattern disposed between the liner semiconductor pattern and the semiconductor substrate, and a capping insulating pattern disposed in the gap region of the liner semiconductor pattern.