Dual-Sided Power Rail Layout for Dense Standard Cells
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Solution Overview
Problem
As standard cell designs become smaller, providing effective connections to components within the cells becomes increasingly difficult, leading to performance issues due to resistances in metal traces and interfaces between diffusion regions and metal traces.
Innovation Solution
Implementing redundant power and control signal connections both above and below transistors in standard cells using topside and backside metal layers, reducing interface resistances and improving performance without increasing cell size or power.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If standard cell size is reduced to increase circuit density, then circuit density improves, but connection access to components becomes more difficult and interface resistances increase
Solution Approach 1:
The patent utilizes the third dimension by implementing power and signal connections from both the topside (above transistors) and backside (below transistors) of the standard cell. This dual-sided connection approach provides multiple access paths to components without increasing the planar footprint, thereby maintaining high circuit density while improving connection reliability and reducing interface resistances through redundant connection paths.
2Quantity of substance
If standard cell size is reduced to increase circuit density, then circuit density improves, but interface resistances increase leading to performance degradation
Solution Approach 1:
By extending connections to both the topside and backside of the standard cell, the patent creates redundant parallel paths for power and signals. This dimensional approach reduces interface resistances by providing multiple connection points between metal traces and diffusion regions, thereby maintaining performance even as cell size is reduced to increase circuit density.
3Reliability
If redundant connections are implemented both above and below transistors, then interface resistances are reduced, but device complexity increases
Solution Approach 1:
The patent exploits the vertical dimension by routing connections from both the topside and backside of the standard cell. This approach reduces interface resistances through redundant paths while avoiding increased planar complexity, as the additional connections are implemented in the vertical dimension rather than requiring more lateral space or complex two-dimensional routing.
Data Source
AI summary
A standard cell layout that may be implemented in FinFET devices or nanosheet FET devices is disclosed. The standard cell layout includes power supply connections from both a topside metal layer and a backside metal layer. A device in the standard cell may be connected to both the topside metal layer and the backside metal layer. Source/drain regions of the device may be connected the metal layers using via contacts within the standard cell layout. Connections to power supply rails from the topside metal layer and the backside metal layer may also be included in the standard cell layout. The rails may be connected to a power supply such that the power supply provides power to the device through both the topside and backside metal layers.