Dual-Sided RDL Electronic Assembly for Compact Routing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The increasing complexity of electronic apparatuses makes it difficult to manufacture active assemblies on substrates, thin films, or glass, leading to increased size and manufacturing costs due to line width and pitch limitations in semiconductor manufacturing, necessitating multi-layered routing structures on conventional circuit substrates.
Innovation Solution
The development of an electronic apparatus with a manufacturing method that includes a first and second metal layer, a PN junction assembly, and a transistor circuit, utilizing single-sided or double-sided redistribution layer (RDL) routing to reduce the number of layers and manufacturing costs, with the electronic assembly being electrically connected to both metal layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If multi-layered routing structure is used on conventional circuit substrate, then routing complexity is resolved, but device size and manufacturing cost increase
Solution Approach 1:
The patent transitions from planar routing to three-dimensional routing by forming conductive patterns on both front and back surfaces of the substrate, with conductive elements extending through the substrate thickness. This vertical dimension utilization allows complex routing without increasing lateral device footprint, directly resolving the contradiction between routing complexity and device size.
Solution Approach 2:
The patent implements nested conductive structures where conductive elements are embedded within the substrate thickness, with front surface patterns, back surface patterns, and through-substrate connections forming a nested three-dimensional network. This nesting approach achieves multi-layered routing functionality while maintaining compact device dimensions.
2Device complexity
If multi-layered routing structure is used on conventional circuit substrate, then routing complexity is resolved, but manufacturing cost increases
Solution Approach 1:
By utilizing the vertical dimension through substrate thickness for conductive connections, the patent achieves complex routing functionality that would traditionally require multiple lateral layers. This dimensional transition simplifies the manufacturing process by reducing the number of sequential deposition and patterning steps needed, thereby lowering manufacturing cost while maintaining routing complexity.
Solution Approach 2:
The patent divides the routing structure into separate front surface and back surface conductive patterns, with through-substrate connections providing vertical integration. This segmentation allows independent optimization and manufacturing of each surface layer, simplifying the overall manufacturing process and reducing costs compared to traditional multi-layer lateral routing.
3Device complexity
If active assembly is manufactured on substrate, then integration is improved, but manufacturing difficulty increases due to delicacy
Solution Approach 1:
The patent embeds conductive elements and electronic assemblies within the substrate structure, creating nested configurations where active components are integrated into the three-dimensional conductive network. This nesting approach achieves high integration while protecting delicate active assemblies within the robust substrate structure, reducing manufacturing difficulty.
Solution Approach 2:
By moving from planar integration to three-dimensional integration within the substrate volume, the patent achieves higher integration density without increasing lateral complexity. The vertical dimension provides additional space for component placement and interconnection, simplifying the manufacturing of integrated assemblies.
Data Source
AI summary
The disclosure provides an electronic apparatus and a manufacturing method thereof. The electronic apparatus includes a first insulating layer, a first metal layer, a second metal layer, and an electronic assembly. The first insulating layer includes a first surface and a second surface opposite to the first surface. The first metal layer has an opening and is formed on the first surface. The second metal layer is formed on the second surface and a projection of the opening on the second surface is overlapped with a projection of the second metal layer on the second surface. The electronic assembly is electrically connected with the first metal layer and the second metal layer.