Dual-Sided Redistribution Package for Fine-Pitch Interconnects

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Solution Overview

Problem

The semiconductor industry faces challenges in achieving high integration density and miniaturization of electronic components while maintaining reliability and reducing warpage in package structures, particularly in forming interconnects with a smaller pitch without increased risk of bridging or process defects.

Innovation Solution

The development of a System-in-Package (SiP) device with an asymmetric dual-sided molded package on a multi-layered redistribution structure, utilizing through-molding vias (TMVs) and varying molding materials and thicknesses on each side to enhance connection density and flexibility, and control thermal expansion to minimize warpage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If interconnects are formed with smaller pitch to increase connection density, then device functionality and integration density improve, but the risk of bridging and process defects increases

Engineering Contradiction:
Improveconnection densityVSAvoidbridging risk
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent employs asymmetric dual-sided molding where the first and second molding materials have different properties (different coefficients of thermal expansion, different viscosities, or different curing characteristics). This asymmetry allows optimization of each side independently - the first molding material can be formulated for fine-pitch interconnect formation with proper flow control to prevent bridging, while the second molding material can be optimized for other requirements. The asymmetric approach enables achieving smaller pitch on the critical side without compromising reliability.

Inventive Principle:
Principle #4Asymmetry

Solution Approach 2:

The patent applies local quality by using different molding materials with specific properties tailored to local requirements. The first molding material is selected or formulated to have specific viscosity, flow characteristics, or curing properties suitable for the fine-pitch interconnect region, while the second molding material has properties suited for its local application. This localized optimization allows the first region to achieve high connection density without bridging, while the second region meets its own requirements.

Inventive Principle:
Principle #3Local quality

2Stability of the object's composition

If different molding materials with different coefficients of thermal expansion are used on each side, then warpage is controlled and minimized, but manufacturing complexity increases

Engineering Contradiction:
Improvewarpage controlVSAvoidmanufacturing complexity
Core Design Contradiction:
Stability of the object's compositionVSDevice complexity

Solution Approach 1:

The patent directly applies thermal expansion principles by selecting first and second molding materials with different coefficients of thermal expansion (CTE) to counterbalance warpage forces. The asymmetric dual-sided molding structure utilizes the differential CTE of the molding materials and underlying substrates to achieve warpage control. By carefully selecting materials with appropriate CTE values, the patent compensates for thermal mismatch and minimizes warpage during manufacturing and operation.

Inventive Principle:
Principle #37Thermal expansion

Solution Approach 2:

The patent employs a counterweight approach to warpage control by using the asymmetric molding structure where the different molding materials and their underlying substrates create opposing forces. The first molding material and substrate combination on one side counterbalances the warpage tendency of the second molding material and substrate combination on the other side. This counterbalancing effect minimizes overall package warpage without requiring additional warpage compensation structures.

Inventive Principle:
Principle #8Anti-weight (Counterweight)

3Productivity

If fan-out package technology with redistribution layers is used to achieve high functional density, then more I/O pads are available, but package size increases

Engineering Contradiction:
Improvefunctional densityVSAvoidpackage area
Core Design Contradiction:
ProductivityVSArea of stationary object

Solution Approach 1:

The patent applies dimensionality change by transitioning from a conventional single-sided fan-out approach to an asymmetric dual-sided molding architecture. The through-molding vias extend vertically through the package structure, utilizing the third dimension (height) to establish electrical connections. This vertical interconnection approach allows I/O pads to be distributed on both the first and second sides of the package, effectively doubling the available connection area without proportionally increasing the package footprint. The redistribution of connections into the vertical dimension enables higher functional density within a compact area.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach allows for the formation of interconnects with a finer pitch, increasing connection density and improving device performance while reducing the risk of bridging and warpage, thereby enhancing yield and reliability.

Implementation Method 1

varying molding materials and thicknesses on each side to enhance connection density and flexibility, and control thermal expansion to minimize warpage

Methodology Applied
Scientific EffectThermal expansion: Thermal Expansion

Data Source

PatentUS20240379648A1Semiconductor Devices and Methods of Manufacturing
Publication Date: 2024.11.14 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20240379648A1 patent drawing
  • US20240379648A1 patent drawing
  • US20240379648A1 patent drawing

AI summary

A method includes forming a redistribution structure including metallization patterns; attaching a semiconductor device to a first side of the redistribution structure; encapsulating the semiconductor device with a first encapsulant; forming openings in the first encapsulant, the openings exposing a metallization pattern of the redistribution structure; forming a conductive material in the openings, comprising at least partially filling the openings with a conductive paste; after forming the conductive material, attaching integrated devices to a second side of the redistribution structure; encapsulating the integrated devices with a second encapsulant; and after encapsulating the integrated devices, forming a pre-solder material on the conductive material.