Dual-Sided Semiconductor Structure for Dense Interconnect Layout
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Solution Overview
Problem
Conventional semiconductor structures face challenges in increasing integration density due to the large distance required for inter-layer isolation, which hinders the improvement of semiconductor performance and results in significant voltage loss and unstable conductive plugs.
Innovation Solution
The first and second transistors are bonded to opposite sides of a substrate, with a first interconnection layer formed on the first transistor and a second interconnection layer on the second transistor, reducing the distance between the transistors and interconnection layers, and incorporating a conductive plug on the substrate surface to minimize voltage loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If transistors are bonded to the same side of the substrate, then interconnection routing is simplified, but the distance between transistors increases and integration density decreases
Solution Approach 1:
The patent applies dimensionality change by bonding transistors to opposite sides of the substrate rather than the same side. This spatial reconfiguration reduces the distance between transistors from lateral separation to vertical proximity through the substrate, significantly increasing integration density while maintaining manageable interconnection complexity through conductive plugs.
2Reliability
If large distance is used for inter-layer isolation, then electrical isolation is improved, but integration degree of semiconductor structures decreases
Solution Approach 1:
The patent extracts the isolation function from large lateral distances and implements it through localized conductive plugs positioned at specific depths. By separating the isolation function from spatial separation, the design achieves electrical isolation without requiring large distances, thereby increasing integration degree while maintaining reliability.
Solution Approach 2:
The patent changes the isolation parameter from lateral distance to vertical depth positioning of conductive plugs. By controlling the depth and position of conductive plugs rather than relying on lateral spacing, the design achieves effective electrical isolation with compact dimensions, improving integration degree while maintaining isolation reliability.
3Reliability
If conductive plugs are placed deeper in the substrate, then electrical connection is achieved, but voltage loss increases and stability decreases
Solution Approach 1:
The patent performs preliminary action by optimizing conductive plug depth and position before final interconnection formation. By pre-positioning conductive plugs at optimal depths and creating intermediate connection structures, the design achieves reliable electrical connection with minimized voltage loss, avoiding the need for excessively deep plugs that would increase energy loss and reduce stability.
Data Source
AI summary
A semiconductor structure and a method for manufacturing the same. The method comprises: providing a substrate comprising a first surface and a second surface opposite to each other; forming, on the first surface, a first transistor structure comprising a first channel layer, a first gate structure disposed on the first channel layer, and a first source-drain epitaxial layer disposed on two lateral sides of the first gate structure; providing, on the second surface, a second transistor structure comprising a second channel layer, a second gate structure disposed on the second channel layer, and a second source-drain epitaxial layer disposed on two lateral sides of the second gate structure; forming, in the second source-drain epitaxial layer and the substrate, a first conductive plug electrically connected to the first source-drain epitaxial layer; and forming a first interconnection layer on the first conductive plug and the second gate structure.