Dual-Sided Semiconductor Package Reducing Thickness
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Solution Overview
Problem
Conventional stacked multichip semiconductor packages face challenges in miniaturization due to the thickness of metal wires and sealing resin required to cover them, leading to increased package thickness and limited thickness reduction.
Innovation Solution
The semiconductor device features a circuit board with first and second main surfaces for mounting semiconductor elements in a stepped configuration, with exposed electrode pads for wire bonding and a sealing resin that minimizes thickness by exposing back surfaces of uppermost semiconductor elements, allowing for electrical connection without increasing the sealing thickness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If metal wires are arranged to pass through the portion exceeding the stack thickness of semiconductor elements, then electrical connection is achieved, but the package thickness increases
Solution Approach 1:
The patent transitions from a conventional single-sided stacked multichip package to a dual-sided package structure where semiconductor elements are mounted on both the front surface and back surface of the circuit substrate. This dimensional change allows wire bonds to be arranged on both surfaces, reducing the need for wires to extend through the entire stack thickness and thereby reducing overall package thickness while maintaining electrical connectivity.
Solution Approach 2:
The patent segments the package structure into front surface elements and back surface elements, with wire bonds distributed across both surfaces. This segmentation allows the wire bonds to be divided into shorter segments on each surface rather than forming long continuous bonds through the entire stack, reducing the thickness contribution of the wiring layer.
2Reliability
If sealing resin thickness is increased to fully cover the wires, then complete sealing is achieved, but the package thickness increases
Solution Approach 1:
By distributing wire bonds on both front and back surfaces of the circuit substrate, the patent reduces the vertical extent of wires that need to be covered by sealing resin. This dimensional redistribution allows for thinner sealing resin while maintaining complete coverage and sealing effectiveness.
3Ease of manufacture
If semiconductor elements are stacked in a single face-up configuration, then wire bonding is enabled, but the package thickness increases
Solution Approach 1:
The patent employs a dual-sided mounting configuration where semiconductor elements are arranged on both the front surface and back surface of the circuit substrate. This spatial redistribution enables wire bonding functionality while reducing the vertical stack height, as wires can be routed on both surfaces rather than extending through the entire thickness.
Solution Approach 2:
The patent creates an asymmetric package structure with different arrangements of semiconductor elements on the front and back surfaces. This asymmetric configuration optimizes the placement of wire bonds and semiconductor elements to minimize the overall package thickness while maintaining all necessary electrical connections.
Data Source
AI summary
A semiconductor device includes a circuit board which has a first main surface having first connection pads, a second main surface having second connection pads, a first opening passing through a vicinity of the first connection pads, and a second opening passing through a vicinity of the second connection pads. A first semiconductor element is mounted in a face-down state on the first main surface of the circuit board. First electrode pads are exposed into the second opening and connected to the second connection pads through the second opening. A second semiconductor element is mounted in a face-up state on the second main surface of the circuit board. Second electrode pads are exposed into the first opening and connected to the first connection pads through the first opening.