Dual-Sided Silicon Integrated Passive Devices for Reduced Series Resistance
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Solution Overview
Problem
Integrated passive devices (IPDs) are limited by having electrical conductors on only one side of the silicon chip, restricting design options and increasing series resistances, which becomes a challenge as integrated circuits shrink to nanometer scales.
Innovation Solution
The development of dual-sided integrated passive devices, where passive components like capacitors and inductors are integrated with electrical conductors on both sides of the silicon wafer, allowing for reduced footprint and improved connectivity between components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If electrical conductors are placed on only one side of the silicon chip, then the manufacturing process is simpler, but the series resistance increases and design flexibility is limited
Solution Approach 1:
The patent transitions from a single-sided conductor configuration to a dual-sided conductor configuration, utilizing the third dimension (depth/thickness of the chip) to place conductors on both the top and bottom surfaces. This dimensional expansion reduces the current path length and associated series resistance while maintaining manufacturing feasibility through adapted fabrication processes.
2Device complexity
If electrical conductors are placed on only one side of the silicon chip, then the device structure is simpler, but design flexibility and connectivity options are restricted
Solution Approach 1:
By utilizing both surfaces of the chip, the patent enables multiple connectivity configurations including top-to-bottom vias, surface-mounted components, and three-dimensional interconnect architectures. This dual-sided approach dramatically increases design flexibility and adaptability while the added structural complexity is managed through systematic fabrication methods.
3Productivity
If the integrated circuit is shrunk to nanometer scales, then the integration density increases, but the series resistance becomes a more significant challenge
Solution Approach 1:
As circuits shrink to nanometer scales, the patent's dual-sided conductor configuration becomes increasingly valuable by providing alternative current paths that bypass the limitations of planar scaling. The vertical dimension offers reduced current path lengths and multiple parallel conduction routes, mitigating the series resistance issues that arise from nanometer-scale integration.
Solution Approach 2:
The patent implements nested conductive structures where conductors are positioned in multiple layers and surfaces, with inner conductors surrounded by outer conductors. This nested configuration provides multiple parallel conduction paths that reduce effective series resistance while maintaining high integration density in the nanometer scale.
Data Source
AI summary
In some embodiments, a system may include an integrated circuit. The integrated circuit may include a substrate including a first surface, a second surface substantially opposite of the first surface, and a first set of electrical conductors coupled to the first surface. The first set of electrical conductors may function to electrically connect the integrated circuit to a circuit board. The integrated circuit may include a semiconductor die coupled to the second surface of the substrate using a second set of electrical conductors. The integrated circuit may include a passive device dimensioned to be integrated with the integrated circuit. The passive device may be positioned between the second surface and at least one of the first set of electrical conductors. The die may be electrically connected to a second side of the passive device. A first side of the passive device may be available to be electrically connected to a second device.