Dual Metal Silicide Layout for Sub-10 nm CMOS Variability
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Solution Overview
Problem
The scaling of features in integrated circuits to the 10 nanometer node and smaller sizes faces challenges due to variability in conventional fabrication processes, limiting further extension into these technology nodes.
Innovation Solution
The implementation of advanced fabrication techniques such as pitch quartering and merged fin pitch quartering approaches to pattern semiconductor fins, along with the use of multi-layer trench isolation structures and fin trim isolation methods, to enhance the precision and density of integrated circuit structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication processes are used, then manufacturing simplicity is maintained, but manufacturing precision deteriorates at 10 nanometer node and smaller sizes
Solution Approach 1:
The fabrication process is divided into multiple discrete stages including pitch doubling, pitch quartering, and merged fin pitch quartering. Each stage performs a specific function (forming mandrels, forming spacers, selective removal) to progressively achieve the final high-precision pattern, breaking down the complex task of creating sub-10nm features into manageable sequential steps
Solution Approach 2:
Mandrel structures are formed in advance before the actual fin structures are created. These preliminary mandrels serve as templates that guide subsequent spacer formation and material deposition, ensuring that the final fin structures achieve the required precision at 10 nanometer node and smaller sizes
2Quantity of substance
If feature size is scaled down to 10 nanometer node and smaller, then device density is improved, but manufacturing precision deteriorates due to process variability
Solution Approach 1:
The spacer structures self-align to the mandrels through conformal deposition processes, automatically establishing precise spacing and positioning without requiring additional alignment steps. This self-service mechanism ensures consistent feature dimensions and spacing even at scaled-down 10 nanometer node sizes, overcoming process variability through inherent process geometry
Solution Approach 2:
The methodology employs multiple pitch multiplication stages (pitch doubling, pitch quartering) that transform the lithographic pattern through controlled parameter changes in material deposition thickness and selective removal. These parameter changes enable precise control of final feature dimensions and spacing, achieving required manufacturing precision while maintaining high device density
Data Source
AI summary
Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a P-type semiconductor device above a substrate and including first and second semiconductor source or drain regions adjacent first and second sides of a first gate electrode. A first metal silicide layer is directly on the first and second semiconductor source or drain regions. An N-type semiconductor device includes third and fourth semiconductor source or drain regions adjacent first and second sides of a second gate electrode. A second metal silicide layer is directly on the third and fourth semiconductor source or drain regions, respectively. The first metal silicide layer comprises at least one metal species not included in the second metal silicide layer.