Dual Silicide FinFET Contact Formation via Crystal Orientation Selectivity
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Solution Overview
Problem
The formation of advanced FinFETs requires precise optimization of contact parameters, particularly in minimizing the presence of second metal silicide in NFET S/D regions and first metal silicide in PFET S/D regions, which poses challenges in achieving high-performance semiconductor devices.
Innovation Solution
A method involving the formation of PFET and NFET fins with specific epitaxial silicon and silicon-germanium layers, followed by deposition of metal silicides and fill metals, ensuring precise control through various processing steps like trench formation, metal deposition, and annealing to achieve the desired silicide formation without cross-contamination.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If different metal silicides are used for NFET and PFET contacts to optimize transistor performance, then device performance is improved, but cross-contamination between silicide types increases
Solution Approach 1:
The patent applies local quality by making the fin structures asymmetric - NFET fins have a first crystal orientation while PFET fins have a second crystal orientation. This local differentiation allows selective silicide formation where each fin type responds differently to the same deposition conditions, enabling contact optimization for each transistor type while preventing cross-contamination through the crystallographic selectivity
Solution Approach 2:
The patent changes the crystal orientation parameter of the fin structures - NFET fins are oriented with <100> direction while PFET fins are oriented with <110> direction. This parameter change creates fundamental differences in silicide formation behavior between the two fin types, allowing selective metal silicide deposition and preventing cross-contamination while maintaining optimal electrical performance for each transistor type
2Productivity
If fin pitch is reduced to increase device density, then packing efficiency is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies local quality by creating distinct crystal orientations in adjacent fin structures - NFET fins with <100> orientation and PFET fins with <110> orientation. This local differentiation provides inherent selectivity that simplifies contact formation processes, allowing precise metal silicide deposition on specific fin types even at reduced pitch, thereby maintaining manufacturing precision while enabling higher device density
Solution Approach 2:
Instead of attempting to form different silicides on identical fin structures through complex masking and selective deposition, the patent inverts the approach by making the fins themselves different through crystal orientation. This inversion simplifies the contact formation process, as the crystallographic difference naturally provides the selectivity needed for precise silicide formation without requiring complex process steps
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of high-performance FinFETs with accurate silicide formation, enhancing the efficiency and density of semiconductor device packing while maintaining optimal performance and reducing production costs.
Implementation Method 1
annealing the semiconductor device, thereby silicidating the first metal and silicidating the second metal
Implementation Method 2
forming a first epitaxial silicon-germanium layer over the epitaxial silicon layer on the PFET fin; forming a second epitaxial silicon-germanium layer over the NFET fin
Data Source
AI summary
At least one method, apparatus and system disclosed herein involves forming semiconductor devices comprising dual silicides in contacts to FinFETs. The semiconductor device may comprise a PFET fin; an NFET fin; a first metal silicide around the NFET fin; a second metal silicide around the PFET fin; and a fill metal around the second metal silicide, above the PFET fin, and above the NFET fin. Methods of forming such devices are also disclosed.