Dual Silicide Formation Using Selective Oxide Thickness Control

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Solution Overview

Problem

Current semiconductor manufacturing processes face challenges in reducing contact resistance between source/drain portions in semiconductor devices, particularly in achieving effective dual silicide formation with minimal patterning processes.

Innovation Solution

A method involving selective oxidation of source/drain portions with different materials to form titanium silicide on n-type and nickel silicide on p-type semiconductor portions, reducing the number of patterning processes required, and using a thickness difference in oxidation layers to control silicide formation, thereby minimizing contact resistance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If multiple patterning processes are used to achieve dual silicide formation, then contact resistance reduction is improved, but manufacturing complexity and critical dimension variation increase

Engineering Contradiction:
Improvecontact resistanceVSAvoidpatterning process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by forming a sacrificial oxide layer on the semiconductor surface before metal deposition. This oxide layer is selectively removed in specific regions to expose the semiconductor, allowing dual silicide formation in a single patterning step rather than multiple steps. The preliminary oxide formation enables subsequent selective metal-silicide reactions without requiring complex multi-step patterning processes.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent uses an oxide layer as an intermediary substance that facilitates dual silicide formation. The oxide layer is formed selectively on certain semiconductor regions, then selectively removed to create patterns for silicide formation. This intermediary oxide approach simplifies the patterning process compared to direct metal patterning methods, reducing both process complexity and critical dimension variations.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If multiple patterning processes are used to achieve dual silicide formation, then contact resistance reduction is improved, but manufacturing time and cost increase

Engineering Contradiction:
Improvecontact resistanceVSAvoidmanufacturing efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent merges multiple patterning operations into a single integrated process sequence. By combining oxide formation, selective oxide removal, and metal deposition into one unified flow, the method achieves dual silicide formation without requiring separate patterning steps for each silicide region. This merging of operations reduces total manufacturing time and improves productivity while maintaining contact resistance benefits.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The preliminary formation of the oxide layer serves as a template that guides subsequent metal deposition and silicide formation. This preliminary structuring eliminates the need for multiple patterning cycles, thereby reducing manufacturing time and increasing production efficiency while still achieving the desired dual silicide configuration for optimal contact resistance.

Inventive Principle:
Principle #10Preliminary action

3Manufacturing precision

If selective oxidation with different thicknesses is performed, then dual silicide formation precision is improved, but process complexity increases

Engineering Contradiction:
Improveoxidation layer thickness controlVSAvoidoxidation process complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent applies local quality by creating oxide layers with different thicknesses in different spatial regions of the semiconductor substrate. By controlling oxidation conditions to produce varying oxide depths across different areas, the method enables selective metal-silicide reactions in specific regions. This local differentiation achieves precise dual silicide formation without requiring complex process sequences, as the thickness variation itself provides the selectivity.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively reduces contact resistance between metal plugs and source/drain portions, enhancing semiconductor device performance while minimizing process complexity and variations in critical dimensions.

Implementation Method 1

introducing an oxidizing agent to oxidize the first and second semiconductor portions

Methodology Applied
Scientific EffectOxidation: Oxidation

Implementation Method 2

introducing a reducing agent to reduce the oxidation layers

Methodology Applied
Scientific EffectReduction: Reduction

Implementation Method 3

a first metal layer is formed such that a portion of the first metal layer reacted with the first semiconductor portion to form a first silicide portion

Methodology Applied
Scientific EffectDiffusion: Diffusion

Data Source

PatentUS20230420565A1Method for forming dual silicide in manufacturing process of semiconductor structure
Publication Date: 2023.12.28 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20230420565A1 patent drawing
  • US20230420565A1 patent drawing
  • US20230420565A1 patent drawing

AI summary

A method for manufacturing a semiconductor structure includes: forming a patterned structure which includes a first semiconductor portion and a second semiconductor portion, the first and second semiconductor portions having different materials; and performing an oxide formation process to oxidize the first and second semiconductor portions such that a first oxidation layer formed on the first semiconductor portion has a thickness less than that of a second oxidation layer formed on the second semiconductor portion.