Dual-Spacer Gate Structure for Overlap Capacitance Control
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Solution Overview
Problem
In the fabrication of high-k metal gate transistors, the overlap capacitance between the gate structure and source/drain region cannot be controlled within a desirable range due to the use of materials with higher dielectric constants for spacers and contact etch stop layers, affecting device performance.
Innovation Solution
A method involving the formation of a gate structure on a substrate, with a first spacer made of silicon carbon nitride (SiCN) adjacent to the gate structure, and a second spacer made of silicon oxycarbonitride (SiOCN) adjacent to the first spacer, followed by the formation of source/drain regions adjacent to the second spacer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If materials with higher dielectric constant are used for spacers and contact etch stop layers, then the gate structure can be formed with adequate spacing and etch stop functionality, but the overlap capacitance between gate structure and source/drain region increases beyond desirable range
Solution Approach 1:
The patent applies local quality by using different dielectric materials with different dielectric constants in different regions. Specifically, a first spacer made of material with lower dielectric constant (e.g., silicon nitride, silicon carbon nitride) is formed adjacent to the gate structure to control overlap capacitance, while a second spacer made of material with higher dielectric constant (e.g., silicon oxide, silicon oxycarbonitride) is formed adjacent to the first spacer to provide etch stop functionality. This spatial differentiation of material properties allows simultaneous optimization of capacitance control and structural stability.
Solution Approach 2:
The patent employs composite materials by combining multiple dielectric layers with different properties in a single spacer structure. The composite spacer structure consists of a first spacer layer with lower dielectric constant and a second spacer layer with higher dielectric constant, creating a functionally integrated structure that simultaneously achieves low overlap capacitance and adequate etch stop capability. This composite approach allows the device to benefit from both material types without requiring separate structures.
2Ease of manufacture
If polysilicon is used as gate material, then the gate structure can be formed with good filling capability, but boron penetration and depletion effect occur which increases equivalent gate dielectric thickness and reduces gate capacitance
Solution Approach 1:
The patent applies parameter changes by transitioning from polysilicon gate material to metal gate material. This fundamental material parameter change eliminates the boron penetration and depletion effects inherent to polysilicon gates, thereby maintaining high gate capacitance and driving force. The metal gate material provides equivalent or superior filling capability while avoiding the electrical degradation issues associated with polysilicon, representing a critical parameter transformation in the gate structure.
Data Source
AI summary
A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a first spacer adjacent to the gate structure, wherein the first spacer comprises silicon carbon nitride (SiCN); forming a second spacer adjacent to the first spacer, wherein the second spacer comprises silicon oxycarbonitride (SiOCN); and forming a source/drain region adjacent to two sides of the second spacer.