Dual Spacer Elements for Semiconductor Gate Stacks
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Solution Overview
Problem
As semiconductor devices are scaled down, the spacing between gate structures decreases, making it difficult for inter-level dielectric layers to effectively fill the regions between adjacent gates, leading to void formation and alignment issues with contacts, which can induce junction leakage.
Innovation Solution
The implementation of a semiconductor device structure that includes a first and second spacer element, where the second spacer element abuts the first spacer and extends partially the height of the gate stack, providing a modified profile that allows the inter-level dielectric layer to fill between gate stacks without voiding, and serving as an etch stop for contact formation, ensuring proper alignment and reducing junction leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the pitch between gate structures is reduced to increase device density, then the number of devices per IC increases, but the inter-level dielectric layer cannot effectively fill the regions between adjacent gates, leading to void formation
Solution Approach 1:
The gate structure is segmented by introducing mandrel structures between adjacent gates. These mandrels divide the continuous ILD filling region into smaller segments, allowing the ILD layer to be deposited and filled more effectively in each segment, thereby preventing void formation while maintaining high device density
Solution Approach 2:
Mandrel structures are introduced as intermediary elements between adjacent gate structures. These mandrels serve as mediators that facilitate the ILD filling process by providing nucleation sites and breaking up the large filling gap into smaller, more manageable regions, thus enabling effective ILD deposition at reduced pitches
2Productivity
If the pitch between gate structures is reduced to increase device density, then more devices fit on the IC, but alignment of contacts to the gate structure becomes more difficult, causing via offset and etching through source/drain regions
Solution Approach 1:
Mandrel structures are formed in advance during the contact alignment process. These pre-formed mandrels serve as alignment references that guide the subsequent contact via formation, ensuring precise alignment even at reduced pitches. The mandrels are positioned beforehand to define the exact location where contacts should be formed
Solution Approach 2:
Mandrel structures act as intermediary alignment references between the gate structure and the contact vias. They provide a physical reference feature that mediates the alignment process, making it easier to accurately position contacts relative to gates at tighter pitch configurations without direct measurement of the small gate dimensions
3Productivity
If contacts are misaligned due to reduced pitch, then device density increases, but etching processes etch through source/drain regions, inducing junction leakage
Solution Approach 1:
Mandrel structures are formed in advance to define precise contact locations before the etching process. This preliminary positioning ensures that subsequent etching operations are accurately guided to the intended contact regions, preventing inadvertent etching through source/drain regions and the resulting junction leakage
Solution Approach 2:
Mandrel structures serve as intermediary protective and guiding features during the contact formation process. They mediate between the contact formation process and the underlying source/drain regions, ensuring that etching is confined to the intended contact holes and does not encroach upon the source/drain regions, thus preventing junction leakage
Data Source
AI summary
The present disclosure describes a semiconductor device including a semiconductor substrate and a gate stack disposed on the semiconductor substrate. A first spacer element is disposed on the substrate abutting the first gate stack. A second spacer element is adjacent the first spacer element. A source/raised drain is provided adjacent the gate stack. A conductive feature (e.g., silicide) is disposed on the source/drain and laterally contacts sidewalls of the second spacer element. In an embodiment, a contact directly interfaces with the second spacer element.