Two-Level Sidewall Spacers for Source/Drain Resistance and Capacitance
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Solution Overview
Problem
As minimum feature size reduces in semiconductor devices, the resistance of source/drain features increases, affecting device performance.
Innovation Solution
A two-level sidewall spacer design is implemented, where an inner sidewall spacer is formed before epitaxial source/drain features and an outer sidewall spacer is formed after, increasing the volume of these features and reducing capacitance between source/drain contacts and the gate electrode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If minimum feature size is reduced to increase integration density, then more components can be integrated into a given chip area, but resistance of source/drain features increases affecting device performance
Solution Approach 1:
The patent introduces a two-level sidewall spacer structure with different thicknesses in vertical and lateral dimensions. The first sidewall spacer has a first thickness and the second sidewall spacer has a second thickness greater than the first thickness, creating a stepped configuration that increases source/drain feature volume without increasing lateral footprint, thus maintaining integration density while reducing resistance
Solution Approach 2:
The patent applies different thickness values to different portions of the sidewall spacers. The first portion (first sidewall spacer) has a first thickness while the second portion (second sidewall spacer) has a second thickness greater than the first thickness. This local variation in geometry optimizes the balance between capacitance reduction and resistance reduction
2Reliability
If source/drain feature volume is increased to reduce resistance, then device performance improves, but capacitance between source/drain contacts and gate electrode increases
Solution Approach 1:
The patent applies different thickness values to different portions of the sidewall spacers. The first portion (first sidewall spacer) has a first thickness while the second portion (second sidewall spacer) has a second thickness greater than the first thickness. This local variation in geometry optimizes the balance between capacitance reduction and resistance reduction
Solution Approach 2:
The sidewall spacer structure is divided into two distinct segments: a first sidewall spacer and a second sidewall spacer with different thicknesses. This segmentation allows each portion to serve different functions - the thinner first spacer reduces capacitance while the thicker second spacer reduces resistance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design improves ion performance and reduces capacitance, enhancing device reliability and mobility while maintaining channel resistance and epitaxial growth margin.
Implementation Method 1
A two-level sidewall spacer design is implemented, where an inner sidewall spacer is formed before epitaxial source/drain features and an outer sidewall spacer is formed after, increasing the volume of these features
Data Source
AI summary
An inner sidewall spacer is formed before the formation of the epitaxial source/drain features and an outer sidewall spacer is formed after the epitaxial source/drain features. The two-level sidewall spacer design increases volume of the epitaxial source/drain features, thus improving ion performance. The thicker sidewall spacers also reduce capacitance between source/drain contacts and the gate electrode. In some embodiments, semiconductor nanosheets may be etched to reduce thickness prior to forming replacement gate structures. Nanosheets with reduced thickness improve device swing performance, reduce DIBL effect without sacrificing the channel resistance and epitaxial growth margin.