Dual Spacer Transistor Gate Structure for Source-Drain Positioning
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Solution Overview
Problem
Conventional transistor fabrication methods face challenges in adjusting the distance between the source/drain and the gate, leading to potential high electric fields and improper placement of source/drain or metal silicide relative to the gate, which affects electrical performance.
Innovation Solution
The use of dual spacers with L-shaped inner spacers is introduced, allowing for adjustable distance between the source/drain and the gate, and preventing the source/drain or metal silicide from being too close to the gate by forming a specific structure with a gate dielectric layer, gate electrode, and spacers, including a first and second dual spacer with L-shaped profiles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single spacer is formed on the gate sidewall, then the fabrication process is simple, but the distance between source/drain and gate cannot be adjusted, leading to high electric field and poor electrical performance
Solution Approach 1:
The single spacer is divided into two separate spacers: a first spacer formed on the gate sidewall and a second spacer formed on the sidewall of the first spacer. This segmentation allows independent control of each spacer's dimensions and materials, enabling precise adjustment of the source/drain to gate distance while maintaining fabrication simplicity through sequential formation processes.
Solution Approach 2:
The first spacer acts as an intermediary structure between the gate and the second spacer. By forming the second spacer on the first spacer rather than directly on the gate, the patent creates a staged spacing system that provides intermediate control over the final source/drain positioning, allowing optimization of electric field distribution and electrical performance.
2Productivity
If the source/drain is placed close to the gate to improve device density, then productivity increases, but high electric field occurs between source/drain and gate, degrading electrical performance
Solution Approach 1:
The patent applies different spacer materials and thicknesses at different locations: the first spacer has specific material composition and thickness, while the second spacer uses different material and thickness parameters. This local differentiation allows the spacer structure to provide optimal spacing in the critical region near the gate while maintaining tighter spacing elsewhere, thus improving device density without creating high electric fields at the gate interface.
3Manufacturing precision
If conventional single spacer fabrication is used, then manufacturing process is simple, but source/drain or metal silicide location cannot be precisely controlled, leading to improper placement
Solution Approach 1:
The first spacer is formed as a preliminary structure that establishes the initial spacing framework before the second spacer is added. This preliminary action creates a staged fabrication process where each spacer formation step builds upon the previous one, allowing precise control over source/drain positioning while maintaining ease of manufacture through standard sequential deposition and etching processes that can be integrated into existing fabrication flows.
Data Source
AI summary
A transistor with dual spacers includes a gate, a first dual spacer and a second inner spacer. The gate is disposed on a substrate, wherein the gate includes a gate dielectric layer and a gate electrode, and the gate dielectric layer protrudes from the gate electrode and covers the substrate. The first dual spacer is disposed on the gate dielectric layer beside the gate, wherein the first dual spacer includes a first inner spacer and a first outer spacer. The second inner spacer having an L-shaped profile is disposed on the gate dielectric layer beside the first dual spacer. The present invention also provides a method of forming said transistor with dual spacers.