Dual-Speed Sequencer for Semiconductor Memory Soft Post Package Repair
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Solution Overview
Problem
In semiconductor memory devices, soft post package repair operations are time-consuming due to the need for sequential and often slow updating of fuse addresses during the replacement of defective word lines or bit lines, which hampers efficiency in repair processes.
Innovation Solution
The semiconductor memory device employs a dual-speed sequencer circuit that increments fuse addresses at high speed before reaching the target memory bank and switches to low speed once within the bank, thereby reducing the overall time required for the soft-post-package-repair operation by skipping unnecessary operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If fuse addresses are updated sequentially at a constant slow speed during soft post package repair, then the repair operation can be performed with simple circuit design, but the repair time becomes excessively long
Solution Approach 1:
The sequencer circuit dynamically changes its operation speed based on the current fuse address value. When the fuse address is less than the target bank start address, the sequencer operates at high speed to quickly reach the target bank. When the fuse address reaches the target bank, the sequencer automatically switches to low speed for precise address matching. This dynamic speed adjustment resolves the contradiction by making the repair process time-efficient without requiring overly complex control circuits.
Solution Approach 2:
The invention changes the operational parameter (clock frequency) of the sequencer circuit based on the fuse address value. By using a first clock frequency when the fuse address is below the target and a second, lower clock frequency when reaching the target, the system optimizes repair time while maintaining circuit simplicity. This parameter change approach allows the sequencer to adapt its behavior to different stages of the repair process.
2Speed
If the sequencer operates at high speed throughout the entire soft post package repair process, then the overall repair time is reduced, but the precision of reaching the target fuse address is compromised
Solution Approach 1:
The sequencer circuit employs periodic action by switching between two operational modes: a high-speed phase for rapid approach to the target bank and a low-speed phase for precise targeting. The transition between these modes occurs at specific fuse address thresholds, creating a periodic pattern of speed adjustment that ensures both rapid progress and accurate positioning during the repair operation.
Solution Approach 2:
The system performs preliminary high-speed operation to quickly reach the vicinity of the target fuse address, then switches to low-speed operation for precise matching. This preliminary action approach allows the majority of the address range to be traversed quickly, reserving the slower, more precise operation only for the critical final matching phase, thereby optimizing both speed and accuracy.
3Productivity
If sequential address updating is used during soft post package repair, then the circuit design remains simple, but the repair efficiency is significantly reduced
Solution Approach 1:
The address update mechanism transitions from a static, uniform-speed approach to a dynamic, variable-speed approach. The sequencer circuit automatically adjusts its update rate based on the relationship between the current fuse address and the target bank start address, enabling high productivity during the approach phase while maintaining simplicity in the control logic through automated threshold-based switching.
Data Source
AI summary
Disclosed herein is an apparatus that includes a fuse array circuit including a plurality of fuse sets each assigned to a corresponding one of a plurality of fuse addresses and configured to operatively store a fuse data, and a first circuit configured to generate and sequentially update a fuse address to sequentially read the fuse data from the plurality of fuse sets. The first circuit is configured to change a frequency of updating the fuse address based on a first signal.