Dual SRAM Pixel Data Storage for Mobile Display Speed
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Solution Overview
Problem
The limited access speed of static random access memory (SRAM) in display controllers of mobile devices hampers higher resolution display applications due to increased pixel data storage requirements as screen sizes and resolutions grow.
Innovation Solution
A system and method utilizing two SRAMs and a data transfer controller to concurrently write and read pixel data in synchronous pairs, allowing independent access and handling of corner pixels, thereby increasing memory access speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If SRAM is used to reduce power consumption, then power consumption is reduced, but memory access speed becomes insufficient for high resolution displays
Solution Approach 1:
The patent divides the pixel data storage into two separate SRAM blocks (first SRAM and second SRAM) that can be accessed concurrently. Each SRAM stores pixel data for specific portions of the display, allowing parallel read operations that effectively double the memory access speed while maintaining the low power consumption characteristics of SRAM.
2Manufacturing precision
If display resolution is increased, then display quality is improved, but pixel data storage requirements increase rapidly
Solution Approach 1:
The patent introduces a temporal dimension to the storage architecture by using frame-based storage with two SRAM blocks. Pixel data is stored in a first frame in the first SRAM and a second frame in the second SRAM, allowing concurrent access to different frames. This dimensional approach enables efficient handling of high-resolution display data without requiring a single oversized memory block.
3Device complexity
If single SRAM is used for pixel data storage, then device complexity is reduced, but memory access speed is limited
Solution Approach 1:
The patent merges two SRAM blocks into a unified storage system with a single controller that manages both SRAMs. This combination allows concurrent access to both SRAMs for writing pixel data in synchronous pairs, effectively doubling the memory access speed while keeping the overall device complexity manageable through centralized control.
Data Source
AI summary
A graphics display device comprises a first and second memory, and a data transfer controller coupled with the first and second memory. In some embodiments, a method of storing pixel data comprises receiving and latching first pixel data associated with a first pixel, receiving second pixel data associated with a second pixel, and concurrently writing the first pixel data in the first memory and the second pixel data in the second memory. In other embodiments, a method of accessing pixel data of an image frame comprises accessing the first and second memory for reading out pixel data of each pair of adjacent pixels, when the image frame has an odd total number of pixels determining whether a final pixel data is in a latched state, and reading out the final pixel data from the data transfer controller when the final pixel data is in the latched state.